[PATCH v9 4/6] iommu/arm-smmu-v3: Add CS_NONE quirk for CONFIG_TEGRA241_CMDQV

[Will Deacon]

On Mon, Jul 08, 2024 at 12:29:28PM +0100, Will Deacon wrote:
> On Fri, Jul 05, 2024 at 11:10:42AM -0700, Nicolin Chen wrote:
> > But if you insist on having an smmu option, we still have to take in the
> > PATCH-3 in this series, enforcing an arm_smmu_cmdq_build_sync_cmd() call
> > in the IRQ handler too.  So, it would eventually look like [attachment].
> 
> With my hacks, I think you can just call arm_smmu_cmdq_build_sync_cmd()
> from the irqhandler and it will work.

Hmm, actually, that will mean we end up using MSIs for the error case on
hardware which supports it, which is a strange change in behaviour.

What does your hardware do if it sees SIG_SEV in a CMD_SYNC? Is it just
a case of failing to generate the event on completion, or does it treat
it as an invalid opcode?

Will