[PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for A64
Jernej Škrabec
jernej.skrabec at gmail.com
Sun Apr 28 09:19:13 PDT 2024
Dne nedelja, 28. april 2024 ob 13:40:35 GMT +2 je Dragan Simic napisal(a):
> Add missing cache information to the Allwinner A64 SoC dtsi, to allow
> the userspace, which includes lscpu(1) that uses the virtual files provided
> by the kernel under the /sys/devices/system/cpu directory, to display the
> proper A64 cache information.
>
> While there, use a more self-descriptive label for the L2 cache node, which
> also makes it more consistent with other SoC dtsi files.
>
> The cache parameters for the A64 dtsi were obtained and partially derived
> by hand from the cache size and layout specifications found in the following
> datasheets and technical reference manuals:
>
> - Allwinner A64 datasheet, version 1.1
> - ARM Cortex-A53 revision r0p3 TRM, version E
>
> For future reference, here's a brief summary of the documentation:
>
> - All caches employ the 64-byte cache line length
> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
> cache and 32 KB of L1 4-way, set-associative data cache
> - The entire SoC has 512 KB of unified L2 16-way, set-associative cache
>
> Signed-off-by: Dragan Simic <dsimic at manjaro.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec at gmail.com>
Best regards,
Jernej
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