[GIT PULL] arm64 fixes for 6.9-rc5

[Catalin Marinas]

Hi Linus,

Please pull the arm64 fixes below. Thanks.

The following changes since commit e3ba51ab24fddef79fc212f9840de54db8fd1685:

  arm64: tlb: Fix TLBI RANGE operand (2024-04-10 18:22:28 +0100)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes

for you to fetch changes up to 50449ca66cc5a8cbc64749cf4b9f3d3fc5f4b457:

  arm64: hibernate: Fix level3 translation fault in swsusp_save() (2024-04-19 16:33:00 +0100)

----------------------------------------------------------------
arm64 fixes:

- Fix a kernel fault during page table walking in huge_pte_alloc() with
  PTABLE_LEVELS=5 due to using p4d_offset() instead of p4d_alloc()

- head.S fix and cleanup to disable the MMU before toggling the
  HCR_EL2.E2H bit when entering the kernel with the MMU on from the EFI
  stub. Changing this bit (currently from VHE to nVHE) causes some
  system registers as well as page table descriptors to be interpreted
  differently, potentially resulting in spurious MMU faults

- Fix translation fault in swsusp_save() accessing MEMBLOCK_NOMAP memory
  ranges due to kernel_page_present() returning true in most
  configurations other than rodata_full == true,
  CONFIG_DEBUG_PAGEALLOC=y or CONFIG_KFENCE=y

----------------------------------------------------------------
Anshuman Khandual (1):
      arm64/hugetlb: Fix page table walk in huge_pte_alloc()

Ard Biesheuvel (2):
      arm64/head: Drop unnecessary pre-disable-MMU workaround
      arm64/head: Disable MMU at EL2 before clearing HCR_EL2.E2H

Yaxiong Tian (1):
      arm64: hibernate: Fix level3 translation fault in swsusp_save()

 arch/arm64/kernel/head.S    | 7 +++++--
 arch/arm64/mm/hugetlbpage.c | 5 ++++-
 arch/arm64/mm/pageattr.c    | 3 ---
 3 files changed, 9 insertions(+), 6 deletions(-)

-- 
Catalin