[PATCH v2 4/4] coresight: etm4x: Fix access to resource selector registers

[Mike Leach]

On Fri, 12 Apr 2024 at 15:27, Suzuki K Poulose <suzuki.poulose at arm.com> wrote:
>
> Resource selector pair 0 is always implemented and reserved. We must not
> touch it, even during save/restore for CPU Idle. Rest of the driver is
> well behaved. Fix the offending ones.
>
> Reported-by: Yabin Cui <yabinc at google.com>
> Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
> Signed-off-by: Suzuki K Poulose <suzuki.poulose at arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index b4b84f2317cd..577cf485e761 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1758,7 +1758,8 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
>                 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
>         }
>
> -       for (i = 0; i < drvdata->nr_resource * 2; i++)
> +       /* Resource selector pair 0 is reserved */
> +       for (i = 2; i < drvdata->nr_resource * 2; i++)
>                 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
>
>         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> @@ -1889,7 +1890,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>                 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
>         }
>
> -       for (i = 0; i < drvdata->nr_resource * 2; i++)
> +       /* Resource selector pair 0 is reserved */
> +       for (i = 2; i < drvdata->nr_resource * 2; i++)
>                 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
>
>         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> --
> 2.34.1
>

Reviewed-by: Mike Leach <mike.leach at linaro.org>


--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK