[PATCH] perf: RISC-V: fix IRQ detection on T-Head C908

[Conor Dooley]

On Fri, Apr 12, 2024 at 02:27:28PM +0800, Yangyu Chen wrote:
> >> IMHO, it may be better to use a new DT property like "riscv,cpu-errata" or
> >> "<vendor>,cpu-errata". It can achieve almost everything like using pseudo
> >> isa. And the only cost I think is a small amount code to parse this.
> > 
> > I suppose we could do that, but accounting for vendor specifics was one
> > of the goals for the property I only just added and that I am suggesting
> > to use here.
> 
> I think there is a simpler way to do that. We use T-Head PMU by default
> for All T-Head CPUs (from mvendor id). Then, to test there is sscofpmf in
> the ISA string being probed by the kernel. If yes, then use scofpmf.
> Otherwise, use T-Head PMU.

I am strongly opposed to doing something like this. Firstly, making it
unconditional is a time-bomb as if T-Head ever ship something without
support then we'll be broken on that platform and have to return to
conditional behaviour. Secondly, we are taking agency away from
hypervisors etc that may not want a guest to use the PMU.

Cheers,
Conor.
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