[PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101

[Alim Akhtar]

Hi Peter

> -----Original Message-----
> From: Peter Griffin <peter.griffin at linaro.org>
> Sent: Thursday, April 4, 2024 5:56 PM
> To: mturquette at baylibre.com; sboyd at kernel.org; robh at kernel.org;
> krzk+dt at kernel.org; conor+dt at kernel.org; vkoul at kernel.org;
> kishon at kernel.org; alim.akhtar at samsung.com; avri.altman at wdc.com;
> bvanassche at acm.org; s.nawrocki at samsung.com; cw00.choi at samsung.com;
> jejb at linux.ibm.com; martin.petersen at oracle.com;
> chanho61.park at samsung.com; ebiggers at kernel.org
> Cc: linux-scsi at vger.kernel.org; linux-phy at lists.infradead.org;
> devicetree at vger.kernel.org; linux-clk at vger.kernel.org; linux-samsung-
> soc at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; tudor.ambarus at linaro.org;
> andre.draszik at linaro.org; saravanak at google.com;
> willmcvicker at google.com; Peter Griffin <peter.griffin at linaro.org>
> Subject: [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101
> 
> Hi folks,
> 
> 
> Question
> ========
> 
> Currently the link comes up in Gear 3 due to ufshcd_init_host_params()
> host_params initialisation. If I update that to use UFS_HS_G4 for
negotiation
> then the link come up in Gear 4. I propose (in a future patch) to use VER
> register offset 0x8 to determine whether to set G4 capability or not (if
major
> version is >= 3).
> 
> The bitfield of VER register in gs101 docs is
> 
> RSVD [31:16] Reserved
> MJR [15:8] Major version number
> MNR [7:4] Minor version number
> VS [3:0] Version Suffix
> 
> Can anyone confirm if other Exynos platforms supported by this driver have
> the same register, and if it conforms to the bitfield described above?
> 

VER (offset 0x8) is standard UFS HCI spec, so all vendor need to have this
(unless something really wrong with the HW)
Yes, Exynos and FSD SoC has these bitfield implemented.
 
> 
> 2.44.0.478.gd926399ef9-goog