[PATCH] arm64: dts: imx8mp: Describe VDD_ARM run and standby voltage for Data Modul i.MX8M Plus eDM SBC

[Marek Vasut]

On 10/9/23 14:36, Shawn Guo wrote:
> On Sun, Oct 08, 2023 at 08:37:34PM +0200, Marek Vasut wrote:
>> On 9/24/23 16:21, Shawn Guo wrote:
>>> On Thu, Aug 31, 2023 at 08:18:50PM +0200, Marek Vasut wrote:
>>>> Describe VDD_ARM (BUCK2) run and standby voltage in DT.
>>>>
>>>> Signed-off-by: Marek Vasut <marex at denx.de>
>>>> ---
>>>> Cc: Conor Dooley <conor+dt at kernel.org>
>>>> Cc: Fabio Estevam <festevam at gmail.com>
>>>> Cc: Frieder Schrempf <frieder.schrempf at kontron.de>
>>>> Cc: Geert Uytterhoeven <geert+renesas at glider.be>
>>>> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
>>>> Cc: Magnus Damm <magnus.damm at gmail.com>
>>>> Cc: Marek Vasut <marex at denx.de>
>>>> Cc: NXP Linux Team <linux-imx at nxp.com>
>>>> Cc: Peng Fan <peng.fan at nxp.com>
>>>> Cc: Pengutronix Kernel Team <kernel at pengutronix.de>
>>>> Cc: Rob Herring <robh+dt at kernel.org>
>>>> Cc: Sascha Hauer <s.hauer at pengutronix.de>
>>>> Cc: Shawn Guo <shawnguo at kernel.org>
>>>> Cc: devicetree at vger.kernel.org
>>>> Cc: linux-arm-kernel at lists.infradead.org
>>>> ---
>>>>    arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts | 2 ++
>>>>    1 file changed, 2 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
>>>> index 13674dc64be9d..d98a040860a48 100644
>>>> --- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
>>>> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
>>>> @@ -362,6 +362,8 @@ buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
>>>>    			};
>>>>    			buck2: BUCK2 {	/* VDD_ARM */
>>>> +				nxp,dvs-run-voltage = <950000>;
>>>> +				nxp,dvs-standby-voltage = <850000>;
>>>
>>> Buck2 is not turned off in DSM on i.MX8MP?
>>
>> It is turned off in SUSPEND/SNVS/OFF , not in IDLE/RUN .
> 
> Right.  But nxp,dvs-standby-voltage specifies the voltage when PMIC
> is in STANDBY mode.  My understanding is that the SoC will be in SUSPEND
> state while PMIC is in STANDBY mode.

I agree

> Is it possible that the SoC in
> IDLE/RUN while PMIC is in STANDBY mode at all?

No, I don't think so, but there's still the PMIC part:

https://www.nxp.com/docs/en/data-sheet/PCA9450.pdf

7.3.7 STANDBY mode
"
PCA9450 transitions to STANDBY mode from RUN mode when
both PMIC_ON_REQ and PMIC_STBY_REQ are driven high. BUCK1
and BUCK3 output voltage is set to BUCK1OUT_DVS1 and
BUCK3OUT_DVS1 and BUCK2 are turned off when DVS_CTRL bit
in each BUCKx_CTRL register is configured to 1.
"

Specifically
"
BUCK2 are turned off when DVS_CTRL bit in each
BUCKx_CTRL register is configured to 1.
"

8.2.19 0x13 BUCK2CTRL
"
4
DVS_CTRL
DVS Control configuration
0b = BUCK voltage is determined by BUCK2VOUT_DVS0 register regardless of 
PMIC_STBY_REQ
1b = DVS control through PMIC_STBY_REQ
"

Notice that the reset-default is '0b' , so unless the PMIC is 
reconfigured, the BUCK2 will stay powered on even in STANDBY/SUSPEND.