[PATCH 3/3] iommu/arm-smmu: re-enable context caching in smmu reset operation

[Bibek Kumar Patro]

On 11/4/2023 5:00 PM, Konrad Dybcio wrote:
> 
> 
> On 11/3/23 22:51, Bibek Kumar Patro wrote:
>> Context caching is re-enabled in the prefetch buffer for Qualcomm SoCs
>> through SoC specific reset ops, which is disabled in the default MMU-500
>> reset ops, but is expected for context banks using ACTLR register to
>> retain the prefetch value during reset and runtime suspend.
>>
>> Signed-off-by: Bibek Kumar Patro <quic_bibekkum at quicinc.com>
>> ---
>>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 26 ++++++++++++++++++----
>>   1 file changed, 22 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c 
>> b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> index 590b7c285299..f342b4778cf1 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> @@ -457,11 +457,29 @@ static int qcom_smmu_def_domain_type(struct 
>> device *dev)
>>       return match ? IOMMU_DOMAIN_IDENTITY : 0;
>>   }
>>
>> +#define ARM_MMU500_ACTLR_CPRE          BIT(1)
>> +
>> +static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
>> +{
>> +    int i;
>> +    u32 reg;
>> +
>> +    arm_mmu500_reset(smmu);
>> +
>> +        for (i = 0; i < smmu->num_context_banks; ++i) {
> This loop deserves a comment above it like
> 
> /* Re-enable context caching after reset */
> 

Ack, thanks for this suggestion, this might help to explain
this addition.
I would incorporate this in next patch.

regards,
Bibek

> Konrad