[PATCH v5 1/2] PCI: dwc: Implement general suspend/resume functionality for L2/L3 transitionse

[Bjorn Helgaas]

On Fri, Jul 28, 2023 at 11:49:28AM -0400, Frank Li wrote:
> On Fri, Jul 28, 2023 at 09:02:38PM +0530, Manivannan Sadhasivam wrote:
> > On Mon, Jul 24, 2023 at 05:58:29PM -0400, Frank Li wrote:
> > > Introduced helper function dw_pcie_get_ltssm to retrieve SMLH_LTSS_STATE.
> > > Added API pme_turn_off and exit_from_l2 for managing L2/L3 state transitions.
> > > ...

> > > +static void dw_pcie_set_dstate(struct dw_pcie *pci, pci_power_t dstate)
> > > +{
> > > +	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_PM);
> > > +	u16 val;
> > > +
> > > +	val = dw_pcie_readw_dbi(pci, offset + PCI_PM_CTRL);
> > > +	val &= ~PCI_PM_CTRL_STATE_MASK;
> > > +	val |= ((u16 __force)dstate) & PCI_PM_CTRL_STATE_MASK;
> > 
> > Why can't just,
> > 
> > val |= dstate;
> 
> fixed a build warning.
> 
> Closes: https://lore.kernel.org/oe-kbuild-all/202307211904.zExw4Q8H-lkp@intel.com/

This is the sparse warning from the lkp URL:

  sparse warnings: (new ones prefixed by >>)
  >> drivers/pci/controller/dwc/pcie-designware-host.c:824:13: sparse: sparse: invalid assignment: |=
  >> drivers/pci/controller/dwc/pcie-designware-host.c:824:13: sparse:    left side has type unsigned int
  >> drivers/pci/controller/dwc/pcie-designware-host.c:824:13: sparse:    right side has type restricted pci_power_t

We have a zillion of those warnings already (try "make C=2 drivers/pci/").

Personally I think it's better to omit the ugly cast and live with the
warning for now.  Someday somebody will figure a better way to use
pci_power_t that will fix all these warnings at once.  I'd rather wait
for that fix than clutter all the uses with casts like this.

Bjorn