[PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration

[Marco Felsch]

On 23-07-25, Marek Vasut wrote:
> The CSI1 PHY reference clock are limited to 125 MHz according to:
> i.MX 8M Nano Applications Processor Reference Manual, Rev. 2, 07/2022
> Table 5-1. Clock Root Table (continued) / page 319
> Slice Index n = 123 .
> 
> Currently those IMX8MN_CLK_CSI1_PHY_REF clock are configured to be
> fed directly from 1 GHz PLL2 , which overclocks them . Instead, drop
> the configuration altogether, which defaults the clock to 24 MHz REF
> clock input, which for the PHY reference clock is just fine.
> 
> Fixes: ae9279f301b5 ("arm64: dts: imx8mn: Add CSI and ISI Nodes")
> Signed-off-by: Marek Vasut <marex at denx.de>

Reviewed-by: Marco Felsch <m.felsch at pengutronix.de>

> ---
> Cc: Adam Ford <aford173 at gmail.com>
> Cc: Conor Dooley <conor+dt at kernel.org>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
> Cc: Li Jun <jun.li at nxp.com>
> Cc: Marco Felsch <m.felsch at pengutronix.de>
> Cc: Marek Vasut <marex at denx.de>
> Cc: NXP Linux Team <linux-imx at nxp.com>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Pengutronix Kernel Team <kernel at pengutronix.de>
> Cc: Richard Cochran <richardcochran at gmail.com>
> Cc: Rob Herring <robh+dt at kernel.org>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Shawn Guo <shawnguo at kernel.org>
> Cc: devicetree at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> ---
>  arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 9869fe7652fca..aa38dd6dc9ba5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -1175,10 +1175,8 @@ mipi_csi: mipi-csi at 32e30000 {
>  				compatible = "fsl,imx8mm-mipi-csi2";
>  				reg = <0x32e30000 0x1000>;
>  				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> -				assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>,
> -						  <&clk IMX8MN_CLK_CSI1_PHY_REF>;
> -				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>,
> -							  <&clk IMX8MN_SYS_PLL2_1000M>;
> +				assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
> +				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
>  				assigned-clock-rates = <333000000>;
>  				clock-frequency = <333000000>;
>  				clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
> -- 
> 2.40.1
> 
>