[PATCH] ARM: dts: imx53-qsb: Improve the parallel display description

[Fabio Estevam]

From: Fabio Estevam <festevam at denx.de>

MX53_PAD_GPIO_1__PWM2_PWMO controls the backlight of the parallel
Seiko display and MX53_PAD_EIM_D24__GPIO3_24 controls the display power.

Reflect that in the devicetree for better description of the board.

Without these entries there is no LCD output on the Seiko display, unless
the bootloader has previously configured these pins.

Signed-off-by: Fabio Estevam <festevam at denx.de>
---
 .../boot/dts/nxp/imx/imx53-qsb-common.dtsi    | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi
index 046254e8d7bb..d80440446473 100644
--- a/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi
@@ -16,6 +16,13 @@ memory at 70000000 {
 		      <0xb0000000 0x20000000>;
 	};
 
+	backlight_parallel: backlight-parallel {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 0 5000000 0>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+	};
+
 	display0: disp0 {
 		compatible = "fsl,imx-parallel-display";
 		pinctrl-names = "default";
@@ -80,6 +87,10 @@ led-user {
 
 	panel {
 		compatible = "sii,43wvf1g";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_display_power>;
+		backlight = <&backlight_parallel>;
+		enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
 
 		port {
 			panel_in: endpoint {
@@ -194,6 +205,12 @@ MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK	0x1c4
 			>;
 		};
 
+		pinctrl_display_power: displaypowergrp {
+			fsl,pins = <
+				MX53_PAD_EIM_D24__GPIO3_24		0x1e4
+			>;
+		};
+
 		pinctrl_esdhc1: esdhc1grp {
 			fsl,pins = <
 				MX53_PAD_SD1_DATA0__ESDHC1_DAT0		0x1d5
@@ -284,6 +301,12 @@ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23	0x5
 			>;
 		};
 
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX53_PAD_GPIO_1__PWM2_PWMO		0x5
+			>;
+		};
+
 		pinctrl_vga_sync: vgasync-grp {
 			fsl,pins = <
 				/* VGA_HSYNC, VSYNC with max drive strength */
@@ -359,6 +382,12 @@ &fec {
 	status = "okay";
 };
 
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
 &sata {
 	status = "okay";
 };
-- 
2.34.1