[PATCH 04/10] clk: mmp: Add Marvell PXA1908 clock driver

[Andy Shevchenko]

On Fri, Jul 21, 2023 at 10:37:46PM +0200, Duje Mihanović wrote:
> Add driver for Marvell PXA1908 clock controller blocks. The SoC has
> numerous clock controller blocks, currently supporting APBC, APBCP, MPMU
> and APMU.

...

> +#include <linux/kernel.h>

Try to avoid using this header without real need.
You have missing a ton of the header inclusions, btw.

> +#include <linux/of_address.h>

> +#define APBC_INDEX_TO_OFFSET(n)	((n - 1) * 4)
> +
> +#define APMU_CLK_GATE_CTRL	0x40
> +#define MPMU_UART_PLL		0x14

...

> +static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
> +	{PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768},
> +	{PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},

HZ_PER_MHZ (from units.h) here and elsewhere?

> +	{PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624000000},
> +	{PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416000000},
> +	{PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499000000},
> +	{PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832000000},
> +	{PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248000000},
> +};

...

> +static struct mmp_clk_factor_masks uart_factor_masks = {
> +	.factor = 2,

> +	.num_mask = 0x1fff,
> +	.den_mask = 0x1fff,

GENMASK() (provided in bits.h).

> +	.num_shift = 16,
> +	.den_shift = 0,
> +};

...

> +static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
> +	{.num = 8125, .den = 1536},	/* 14.745MHz */
> +};

Can this struct be dropped in favour of struct u32_fract (from math.h)?

...

> +	pxa_unit->apbc_base = of_iomap(np, 0);
> +	if (!pxa_unit->apbc_base) {
> +		pr_err("failed to map apbc registers\n");

Haven't noticed if you are using pr_fmt().

> +		kfree(pxa_unit);
> +		return;
> +	}

-- 
With Best Regards,
Andy Shevchenko