[PATCH 07/27] arm64: Add missing BRB/CFP/DVP/CPP instructions

[Miguel Luis]

Hi Marc,

> On 12 Jul 2023, at 14:57, Marc Zyngier <maz at kernel.org> wrote:
> 
> HFGITR_EL2 traps a bunch of instructions for which we don't have
> encodings yet. Add them.
> 
> Signed-off-by: Marc Zyngier <maz at kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 7 +++++++
> 1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 9dfd127be55a..e2357529c633 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -737,6 +737,13 @@
> #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
> #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
> 
> +/* Misc instructions */
> +#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
> +#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
> +#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
> +#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
> +#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
> +

As documented in DDI0487J.a

Reviewed-by: Miguel Luis <miguel.luis at oracle.com>

Miguel

> /* Common SCTLR_ELx flags. */
> #define SCTLR_ELx_ENTP2 (BIT(60))
> #define SCTLR_ELx_DSSBS (BIT(44))
> -- 
> 2.34.1
>