[PATCH] soc: imx: imx8mp-blk-ctrl: register HSIO PLL clock as bus_power_dev child

[Yannic Moog]

Hello Lucas,

thank you for fixing this issue.

On Mon, 2023-07-17 at 16:54 +0200, Lucas Stach wrote:
> The blk-ctrl device is deliberately placed outside of the GPC power
> domain as it needs to control the power sequencing of the blk-ctrl
> domains together with the GPC domains.
> 
> Clock runtime PM works by operating on the clock parent device, which
> doesn't translate into the neccessary GPC power domain action if the
> clk parent is not part of the GPC power domain. Use the
> bus_power_device
> as the parent for the clock to trigger the proper GPC domain actions
> on
> clock runtime power management.
> 
> Fixes: 2cbee26e5d59 ("soc: imx: imx8mp-blk-ctrl: expose high
> performance PLL clock")
> Reported-by: Yannic Moog <Y.Moog at phytec.de>
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> ---
>  drivers/soc/imx/imx8mp-blk-ctrl.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c
> b/drivers/soc/imx/imx8mp-blk-ctrl.c
> index 870aecc0202a..1c1fcab4979a 100644
> --- a/drivers/soc/imx/imx8mp-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
> @@ -164,7 +164,7 @@ static int imx8mp_hsio_blk_ctrl_probe(struct
> imx8mp_blk_ctrl *bc)
>         clk_hsio_pll->hw.init = &init;
>  
>         hw = &clk_hsio_pll->hw;
> -       ret = devm_clk_hw_register(bc->dev, hw);
> +       ret = devm_clk_hw_register(bc->bus_power_dev, hw);
>         if (ret)
>                 return ret;
>  

Tested-by: Yannic Moog <y.moog at phytec.de>

Yannic