[PATCH 4/6] clk: qcom: Add NSS clock Controller driver for IPQ9574

[Devi Priya]

On 7/13/2023 11:07 AM, Simon Horman wrote:
> On Tue, Jul 11, 2023 at 03:05:27PM +0530, Devi Priya wrote:
>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
>> devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy at quicinc.com>
> 
> ...
> 
>> +static const struct qcom_reset_map nss_cc_ipq9574_resets[] = {
>> +	[NSS_CC_CE_BCR] = { 0x28400, 0 },
>> +	[NSS_CC_CLC_BCR] = { 0x28600, 0 },
>> +	[NSS_CC_EIP197_BCR] = { 0x16004, 0 },
>> +	[NSS_CC_HAQ_BCR] = { 0x28300, 0 },
>> +	[NSS_CC_IMEM_BCR] = { 0xe004, 0 },
>> +	[NSS_CC_MAC_BCR] = { 0x28100, 0 },
>> +	[NSS_CC_PPE_BCR] = { 0x28200, 0 },
>> +	[NSS_CC_UBI_BCR] = { 0x28700, 0 },
>> +	[NSS_CC_UNIPHY_BCR] = { 0x28900, 0 },
>> +	[UBI3_CLKRST_CLAMP_ENABLE] = { 0x28A04, 9 },
>> +	[UBI3_CORE_CLAMP_ENABLE] = { 0x28A04, 8 },
>> +	[UBI2_CLKRST_CLAMP_ENABLE] = { 0x28A04, 7 },
>> +	[UBI2_CORE_CLAMP_ENABLE] = { 0x28A04, 6 },
>> +	[UBI1_CLKRST_CLAMP_ENABLE] = { 0x28A04, 5 },
>> +	[UBI1_CORE_CLAMP_ENABLE] = { 0x28A04, 4 },
>> +	[UBI0_CLKRST_CLAMP_ENABLE] = { 0x28A04, 3 },
>> +	[UBI0_CORE_CLAMP_ENABLE] = { 0x28A04, 2 },
>> +	[NSSNOC_NSS_CSR_ARES] = { 0x28A04, 1 },
>> +	[NSS_CSR_ARES]  { 0x28A04, 0 },
> 
> Hi Devi,
> 
> There appears to be an '=' missing in the line above.

Hi Simon,
Thanks for catching it! will update it in V2.

Regards,
Devi Priya
> 
> ...