imx8mp phyboard-pollux hsio-blk-ctrl boot hang

[Lucas Stach]

Hi Yannic,

Am Donnerstag, dem 13.07.2023 um 13:08 +0000 schrieb Yannic Moog:
> Hello Lucas, NXP Team,
> 
> We noticed that for the phyboard-pollux, commit
> 2cbee26e5d592da942a995ddee78ea3eb97ad2fa (soc: imx: imx8mp-blk-ctrl:
> expose high performance PLL clock) breaks successful boot.
> Furthermore, when passing clk_ignore_unused to kernel command line, the
> board does boot successfully, with the afforementioned patch applied.
> Also, when disabling the hsio_blk_ctrl node in the imx8mp.dtsi and thus
> the driver, the board does boot as well.
> FYI, we do not currently have usb and pcie supported upstream.
> 
> Thus leading to my question:
> What is the best way to deal with this problem?
> To me it appears that some clock is being disabled while some other
> consumer relies on it.
> 

That is very unlikely as this clock is exclusively used by the PCIe PHY
and optionally the USB PHY. As you don't support any of those devices,
there shouldn't be any hidden consumer.

>  How can I find out who that is or how I can
> prevent the clock from being deemed unused and thus disabled?

However, I now see a potential problem: if the HSIO GPC power domain is
powered down at clk_disable_unused time, we might not properly wake it
to access the PLL registers. I'll take a look at this and will get back
to you.

Regards,
Lucas