[PATCH 1/2] PCI: j721e: Allow async probe

[Li Chen]

 ---- On Tue, 11 Jul 2023 14:16:01 +0800  Verma, Achal  wrote --- 
 > 
 > 
 > On 7/7/2023 7:53 AM, Li Chen wrote:
 > > From: Li Chen lchen at ambarella.com>
 > > 
 > > I observed that on Ambarella SoC, which also utilizes
 > > the Cadence controller, the boot time increases by 1
 > > second when no endpoints (including switch) are connected
 > > to PCIe. This increase is caused by cdns_pcie_host_wait_for_link.
 > > 
 > > Enabling async probe can eliminate this boot time increase.
 > > 
 > > I guess j721e also has this issue.
 > I have tested this along with:
 > https://lore.kernel.org 
 > /all/1892e2ae15f.f7e5dc061620757.4339091752690983066 at linux.beauty/
 > 
 > But I couldn't find second patch in this series.

Sorry for my mistake, the second patch is just the link you mentioned(https://lore.kernel.org/all/1892e2ae15f.f7e5dc061620757.4339091752690983066@linux.beauty/), I accidentally removed its "2/2" prefix.

Should I post v2 to fix the subject issue?

 > > 
 > > Signed-off-by: Li Chen lchen at ambarella.com>
 > Tested-by: Achal Verma a-verma1 at ti.com>
 > > ---
 > >   drivers/pci/controller/cadence/pci-j721e.c | 1 +
 > >   1 file changed, 1 insertion(+)
 > > 
 > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
 > > index e70213c9060a..660c13bdb606 100644
 > > --- a/drivers/pci/controller/cadence/pci-j721e.c
 > > +++ b/drivers/pci/controller/cadence/pci-j721e.c
 > > @@ -561,6 +561,7 @@ static struct platform_driver j721e_pcie_driver = {
 > >           .name    = "j721e-pcie",
 > >           .of_match_table = of_j721e_pcie_match,
 > >           .suppress_bind_attrs = true,
 > > +        .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 > >       },
 > >   };
 > >   builtin_platform_driver(j721e_pcie_driver);
 > 

Regards,
Li