[PATCH v3 8/8] clk: sunxi-ng: a64: select closest rate for pll-video0
Maxime Ripard
maxime at cerno.tech
Mon Jul 3 00:50:05 PDT 2023
On Sun, Jul 02, 2023 at 07:55:27PM +0200, Frank Oltmanns wrote:
> @@ -541,7 +542,7 @@ static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
> static const u8 tcon1_table[] = { 0, 2, };
> static struct ccu_div tcon1_clk = {
> .enable = BIT(31),
> - .div = _SUNXI_CCU_DIV(0, 4),
> + .div = _SUNXI_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ROUND_CLOSEST),
> .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table),
> .common = {
> .reg = 0x11c,
> @@ -549,6 +550,7 @@ static struct ccu_div tcon1_clk = {
> tcon1_parents,
> &ccu_div_ops,
> CLK_SET_RATE_PARENT),
> + .features = CCU_FEATURE_CLOSEST_RATE,
> },
> };
I'm not super comfortable with having to set it twice for dividers (or
composite clocks). Could we set CLK_DIVIDER_ROUND_CLOSEST automatically
if CCU_FEATURE_CLOSEST_RATE is set?
I'm guessing we would need it for muxes as well?
Maxime
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