PHY issue with SJA1105Q/DP84849I Design

[Vladimir Oltean]

On Sat, Dec 30, 2023 at 01:48:38AM +0530, Jagan Teki wrote:
> On Fri, Dec 29, 2023 at 8:55 PM Vladimir Oltean <olteanv at gmail.com> wrote:
> > Why all these combinations? You don't know which switch port is which?
> 
> This is where I get confused in the first place. I didn't find proper
> information on binding about how the physical pin-out is to be
> configured in DT ports or maybe I didn't understand properly.
> 
> As per schematics.
> Pin MII0_RXD0-D3/TXD0-D3 is connected to PROC_MII0_RXD0-D3/TXD0-D3
> this would be fec0.
> Pin MII1_RXD0-D3/TXD0-D3 is connected to PHY_MII1_RXD0-D3/TXD0-D3 this
> would be ethphy0.
> Pin MII2_RXD0-D3/TXD0-D3 is connected to PHY_MII2_RXD0-D3/TXD0-D3 this
> would be ethphy1.
> Pin MII3_RXD0-D3/TXD0-D3 is grounded
> Pin MII4_RXD0-D3/TXD0-D3 is grounded
> 
> So, I did use the above 3 combinations and assumed fec0 is always a
> port4 based on existing DTS in the tree. Please let me know which
> configuration is proper as per schematic connections.

With this switch, any port can be a CPU port. The CPU port selection
from existing, unrelated upstream boards has no influence upon yours.

The pin naming in "MII0_RXD/TXD" follows the same numbering scheme as
"port at 0" etc. The SJA1105PQRS.pdf datasheet should tell you as much.
So your CPU port should be the "port at 0" node and not "port at 4". The
switch "port at 3" and "port at 4" sound like they should be the ones with
status = "disabled".

> > If you are truly using MII, then you should remove the RGMII delay
> > properties, and since you are using a 6.1 kernel - hence after kernel
> > commit 5d645df99ac6 ("net: dsa: sja1105: determine PHY/MAC role from PHY
> > interface type") - you should be using phy-mode = "rev-mii" to put this
> > port in MII PHY ("RevMII") mode - to interoperate with the FEC in MII
> > MAC mode.
> 
> Okay, I will remove RGMII delay. is phy-mode = "rev-mii" applicable to
> all ports or only for fec port4?

Use phy-mode = "rev-mii" for the switch port going to the FEC, and
phy-mode = "mii" for the switch ports going to MII PHYs (and for the FEC
itself).

> > You can also use the RX counters to determine which switch port is which
> > (but the phy-handle of each port to each PHY needs to be correct).
> 
> RX counters in ethtool you mean?

Yes.