[PATCH v3 02/27] arm64: Add missing ERX*_EL1 encodings

[Jing Zhang]

On Tue, Aug 8, 2023 at 4:47 AM Marc Zyngier <maz at kernel.org> wrote:
>
> We only describe a few of the ERX*_EL1 registers. Add the missing
> ones (ERXPFGF_EL1, ERXPFGCTL_EL1, ERXPFGCDN_EL1, ERXMISC2_EL1 and
> ERXMISC3_EL1).
>
> Reviewed-by: Eric Auger <eric.auger at redhat.com>
> Signed-off-by: Marc Zyngier <maz at kernel.org>
> Reviewed-by: Miguel Luis <miguel.luis at oracle.com>
> Acked-by: Catalin Marinas <catalin.marinas at arm.com>
> Reviewed-by: Zenghui Yu <yuzenghui at huawei.com>
> ---
>  arch/arm64/include/asm/sysreg.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 85447e68951a..ed2739897859 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -229,8 +229,13 @@
>  #define SYS_ERXCTLR_EL1                        sys_reg(3, 0, 5, 4, 1)
>  #define SYS_ERXSTATUS_EL1              sys_reg(3, 0, 5, 4, 2)
>  #define SYS_ERXADDR_EL1                        sys_reg(3, 0, 5, 4, 3)
> +#define SYS_ERXPFGF_EL1                        sys_reg(3, 0, 5, 4, 4)
> +#define SYS_ERXPFGCTL_EL1              sys_reg(3, 0, 5, 4, 5)
> +#define SYS_ERXPFGCDN_EL1              sys_reg(3, 0, 5, 4, 6)
>  #define SYS_ERXMISC0_EL1               sys_reg(3, 0, 5, 5, 0)
>  #define SYS_ERXMISC1_EL1               sys_reg(3, 0, 5, 5, 1)
> +#define SYS_ERXMISC2_EL1               sys_reg(3, 0, 5, 5, 2)
> +#define SYS_ERXMISC3_EL1               sys_reg(3, 0, 5, 5, 3)
>  #define SYS_TFSR_EL1                   sys_reg(3, 0, 5, 6, 0)
>  #define SYS_TFSRE0_EL1                 sys_reg(3, 0, 5, 6, 1)
>
> --
> 2.34.1
>
>

Reviewed-by: Jing Zhang <jingzhangos at google.com>