[PATCH v2 15/19] arm64: add encodings of PIRx_ELx registers

Mark Brown broonie at kernel.org
Tue Apr 18 07:02:15 PDT 2023


On Thu, Apr 13, 2023 at 12:05:09PM +0100, Joey Gouly wrote:

> +/*
> + * PIIndex[3:0] encoding (Permission Indirection Extension)
> + */
> +#define PTE_PI_IDX_0	6
> +#define PTE_PI_IDX_1	51
> +#define PTE_PI_IDX_2	53
> +#define PTE_PI_IDX_3	54

FWIW I locally updated this to:

-#define PTE_PI_IDX_0   6
-#define PTE_PI_IDX_1   51
-#define PTE_PI_IDX_2   53
-#define PTE_PI_IDX_3   54
+#define PTE_PI_IDX_0   6       /* AP[1], USER */
+#define PTE_PI_IDX_1   51      /* DBM */
+#define PTE_PI_IDX_2   53      /* PXN */
+#define PTE_PI_IDX_3   54      /* UXN */

for ease of reference, it is in your cover letter and of course the
architecture but it's handy to have to hand in the code.

> +#define PIE_E0	( \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_X_O) | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX)  | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RWX) | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)   | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW))
> +
> +#define PIE_E1	( \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_NONE_O) | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R)      | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RW)     | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)      | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW)     | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_ROX),    PIE_RX)     | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_RO),     PIE_R)      | \
> +	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL),        PIE_RW))

I also added this for future reference:

+/*
+ * Page types used via Page Table Indirection (PTI).  PTE uses the
+ * USER, DBM, PXN and UXN bits to to generate an index which is used
+ * to look up the actual permission in PIR_ELx and PIRE0_EL1.  We
+ * define combinations we use on non-PTI systems with the same
+ * encoding, for convenience these are listed here as comments as are
+ * the unallocated encodings.
+ */
+
+/* 0: PAGE_DEFAULT                                                  */
+/* 1:                      PTE_USER                                 */
+/* 2:                      PTE_WRITE                                */
+/* 3:                      PTE_WRITE | PTE_USER                     */
+/* 4: PAGE_EXECONLY        PTE_PXN                                  */
+/* 5: PAGE_READONLY_EXEC   PTE_PXN | PTE_USER                       */
+/* 6:                      PTE_PXN | PTE_WRITE                      */
+/* 7:                      PTE_PXN | PTE_WRITE | PTE_USER           */
+/* 8: PAGE_KERNEL_ROX      PTE_UXN                                  */
+/* 9:                      PTE_UXN | PTE_USER                       */
+/* a: PAGE_KERNEL_EXEC     PTE_UXN | PTE_WRITE                      */
+/* b:                      PTE_UXN | PTE_WRITE | PTE_USER           */
+/* c: PAGE_KERNEL_RO       PTE_UXN | PTE_PXN                        */
+/* d: PAGE_READONLY        PTE_UXN | PTE_PXN | PTE_USER             */
+/* e: PAGE_KERNEL          PTE_UXN | PTE_PXN | PTE_WRITE            */
+/* f: PAGE_SHARED          PTE_UXN | PTE_PXN | PTE_WRITE | PTE_USER */

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