[PATCH v2 4/4] pwm: meson: make full use of common clock framework

[Thierry Reding]

On Tue, Apr 11, 2023 at 09:48:46PM +0200, Martin Blumenstingl wrote:
> On Tue, Apr 11, 2023 at 9:26 PM Heiner Kallweit <hkallweit1 at gmail.com> wrote:
> [...]
> > +               init.name = name;
> > +               init.ops = &clk_gate_ops;
> > +               init.flags = CLK_SET_RATE_PARENT;
> As much as I don't want it: I think we need CLK_IGNORE_UNUSED here as well :-(
> On GXBB, GXL and GXM SoCs the board design typically uses PWM
> regulators (like the boards using 32-bit SoCs as well as newer boards
> using G12A or later SoCs).
> This means: if we enable that PWM controller and one of the channels
> is firmware managed and the other isn't then we can end up disabling
> the clock - taking away VCCK (which supplies the CPU) or VDDEE (which
> supplies GPU and various other components).
> I'd be happy if there are other suggestions around this though.

What exactly does "firmware managed" mean? Typically we describe all
supplies in DT to avoid these kinds of workarounds. If VCCK and/or VDDEE
are PWM-controlled regulators that should never be turned off, can they
not simply be added to device tree and marked as "always-on"? That would
propagate to the PWM and make sure the corresponding clock remains
enabled.

Thierry
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