[RFC PATCH 31/38] arm64/sysreg: Convert ID_PFR2_EL1 to automatic generation

[James Morse]

Convert ID_PFR1_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.

Signed-off-by: James Morse <james.morse at arm.com>
---
 arch/arm64/include/asm/sysreg.h |  4 ----
 arch/arm64/tools/sysreg         | 16 ++++++++++++++++
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 94cc887c9e9b..4fd4dfd0c32b 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -165,7 +165,6 @@
 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
 
-#define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)
 #define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
 #define SYS_ID_DFR1_EL1			sys_reg(3, 0, 0, 3, 5)
 #define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)
@@ -694,9 +693,6 @@
 #define ID_DFR0_EL1_CopSDbg_SHIFT	4
 #define ID_DFR0_EL1_CopDbg_SHIFT	0
 
-#define ID_PFR2_EL1_SSBS_SHIFT		4
-#define ID_PFR2_EL1_CSV3_SHIFT		0
-
 #define MVFR0_EL1_FPRound_SHIFT		28
 #define MVFR0_EL1_FPShVec_SHIFT		24
 #define MVFR0_EL1_FPSqrt_SHIFT		20
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 7aa971ba8aa0..7259fdf09e4b 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -605,6 +605,22 @@ Enum	3:0	SpecSEI
 EndEnum
 EndSysreg
 
+Sysreg ID_PFR2_EL1	3	0	0	3	4
+Res0	63:12
+Enum	11:8	RAS_frac
+	0b0000	NI
+	0b0001	RASv1p1
+EndEnum
+Enum	7:4	SSBS
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	3:0	CSV3
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+EndSysreg
+
 Sysreg	ID_AA64PFR0_EL1	3	0	0	4	0
 Enum	63:60	CSV3
 	0b0000	NI
-- 
2.30.2