[RFC PATCH 28/38] arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation

[James Morse]

Convert ID_ISAR6_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.

Signed-off-by: James Morse <james.morse at arm.com>
---
 arch/arm64/include/asm/sysreg.h | 10 ----------
 arch/arm64/tools/sysreg         | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 36a01baec0c6..4e9cb26bd60a 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -173,8 +173,6 @@
 #define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)
 #define SYS_ID_MMFR5_EL1		sys_reg(3, 0, 0, 3, 6)
 
-#define SYS_ID_ISAR6_EL1		sys_reg(3, 0, 0, 2, 7)
-
 #define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
 #define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
 #define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
@@ -688,14 +686,6 @@
 
 #define ID_DFR1_EL1_MTPMU_SHIFT		0
 
-#define ID_ISAR6_EL1_I8MM_SHIFT		24
-#define ID_ISAR6_EL1_BF16_SHIFT		20
-#define ID_ISAR6_EL1_SPECRES_SHIFT	16
-#define ID_ISAR6_EL1_SB_SHIFT		12
-#define ID_ISAR6_EL1_FHM_SHIFT		8
-#define ID_ISAR6_EL1_DP_SHIFT		4
-#define ID_ISAR6_EL1_JSCVT_SHIFT	0
-
 #define ID_MMFR5_EL1_ETS_SHIFT		0
 
 #define ID_PFR0_EL1_DIT_SHIFT		24
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 1d7885130514..eba4bf0d1479 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -454,6 +454,38 @@ Enum	3:0	SEVL
 EndEnum
 EndSysreg
 
+Sysreg ID_ISAR6_EL1	3	0	0	2	7
+Res0	63:28
+Enum	27:24	I8MM
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	23:20	BF16
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	19:16	SPECRES
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	15:12	SB
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	11:8	FHM
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	7:4	DP
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	3:0	JSCVT
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+EndSysreg
+
 Sysreg ID_MMFR4_EL1	3	0	0	2	6
 Res0	63:32
 Enum	31:28	EVT
-- 
2.30.2