[boot-wrapper PATCH] aarch64: enable access to HCRX_EL2
Mark Rutland
mark.rutland at arm.com
Fri Sep 30 06:25:46 PDT 2022
On Tue, Sep 27, 2022 at 03:23:43PM +0100, Kristina Martsenko wrote:
> Allow EL2 to access the HCRX_EL2 register which provides hypervisor
> controls similarly to HCR_EL2.
>
> Signed-off-by: Kristina Martsenko <kristina.martsenko at arm.com>
Thanks; applied.
Mark.
> ---
> arch/aarch64/include/asm/cpu.h | 3 +++
> arch/aarch64/init.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
> index 69dfcd5..d063948 100644
> --- a/arch/aarch64/include/asm/cpu.h
> +++ b/arch/aarch64/include/asm/cpu.h
> @@ -49,6 +49,7 @@
> #define SCR_EL3_FGTEN BIT(27)
> #define SCR_EL3_ECVEN BIT(28)
> #define SCR_EL3_TME BIT(34)
> +#define SCR_EL3_HXEn BIT(38)
> #define SCR_EL3_EnTP2 BIT(41)
>
> #define HCR_EL2_RES1 BIT(1)
> @@ -70,6 +71,8 @@
> #define ID_AA64MMFR0_EL1_FGT BITS(59, 56)
> #define ID_AA64MMFR0_EL1_ECV BITS(63, 60)
>
> +#define ID_AA64MMFR1_EL1_HCX BITS(43, 40)
> +
> #define ID_AA64PFR1_EL1_MTE BITS(11, 8)
> #define ID_AA64PFR1_EL1_SME BITS(27, 24)
> #define ID_AA64PFR0_EL1_SVE BITS(35, 32)
> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
> index db73b58..471e234 100644
> --- a/arch/aarch64/init.c
> +++ b/arch/aarch64/init.c
> @@ -61,6 +61,9 @@ void cpu_init_el3(void)
> if (mrs_field(ID_AA64MMFR0_EL1, ECV) >= 2)
> scr |= SCR_EL3_ECVEN;
>
> + if (mrs_field(ID_AA64MMFR1_EL1, HCX))
> + scr |= SCR_EL3_HXEn;
> +
> if (mrs_field(ID_AA64PFR1_EL1, MTE) >= 2)
> scr |= SCR_EL3_ATA;
>
>
> base-commit: 6a0fc40035f9bb581054eb26fbac3c659cfa99b2
> --
> 2.25.1
>
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