[PATCH] ACPI/IORT: Update SMMUv3 DeviceID support

Nicolin Chen nicolinc at nvidia.com
Thu Sep 29 09:23:37 PDT 2022


On Thu, Sep 29, 2022 at 11:22:13AM +0100, Robin Murphy wrote:
> External email: Use caution opening links or attachments
> 
> 
> On 2022-09-29 00:55, Nicolin Chen wrote:
> > On Wed, Sep 28, 2022 at 08:21:26PM +0100, Robin Murphy wrote:
> > > External email: Use caution opening links or attachments
> > > 
> > > 
> > > IORT E.e now allows SMMUv3 nodes to describe the DeviceID for MSIs
> > > independently of wired GSIVs, where the previous oddly-restrictive
> > > definition meant that an SMMU without PRI support had to provide a
> > > DeviceID even if it didn't support MSIs either. Support this, with
> > > the usual temporary flag definition while the real one is making
> > > its way through ACPICA.
> > > 
> > > Signed-off-by: Robin Murphy <robin.murphy at arm.com>
> > 
> > All the indentations in this patch are using white spaces vs. tabs,
> 
> That must be something at your end - they're definitely tabs here, and
> the copy in the lore archives looks right too.

Oh...it is something wrong on my side. The patch should be fine.

Sorry for the confusion.



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