[PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support

[Matt Ranostay]

On Fri, Sep 23, 2022 at 02:50:19PM +0530, Kishon Vijay Abraham I wrote:
> Hi Matt,
> 
> On 10/09/22 1:46 am, Matt Ranostay wrote:
> > Increase LANE_COUNT_MASK to two-bit field that allows selection of
> > 4x lane PCIe which was previously limited to 2x lane support.
> > 
> > Cc: Kishon Vijay Abraham I <kishon at ti.com>
> > Signed-off-by: Matt Ranostay <mranostay at ti.com>
> > Signed-off-by: Vignesh Raghavendra <vigneshr at ti.com>
> > ---
> >   drivers/pci/controller/cadence/pci-j721e.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> > index a82f845cc4b5..62c2c70256b8 100644
> > --- a/drivers/pci/controller/cadence/pci-j721e.c
> > +++ b/drivers/pci/controller/cadence/pci-j721e.c
> > @@ -43,7 +43,7 @@ enum link_status {
> >   };
> >   #define J721E_MODE_RC			BIT(7)
> > -#define LANE_COUNT_MASK			BIT(8)
> > +#define LANE_COUNT_MASK			GENMASK(9, 8)
> 
> The MASK value as well has to be specific to platforms. For J721E, it is 1
> bit only.
>

Noted. Will revise in next version of the patchset.

- Matt

> Thanks,
> Kishon
> 
> >   #define LANE_COUNT(n)			((n) << 8)
> >   #define GENERATION_SEL_MASK		GENMASK(1, 0)
> >