[PATCH] clk: imx: imx6sx: remove the SET_RATE_PARENT flag for QSPI clocks

[Fabio Estevam]

Hi Han Xu,

On Wed, Sep 14, 2022 at 5:51 PM Fabio Estevam <festevam at gmail.com> wrote:
>
> Hi Han Xu,
>
> On Wed, Sep 14, 2022 at 5:11 PM Han Xu <han.xu at nxp.com> wrote:
> >
> > There is no dedicate parent clock for QSPI so SET_RATE_PARENT flag
> > should not be used. For instance, the default parent clock for QSPI is
> > pll2_bus, which is also the parent clock for quite a few modules, such
> > as MMDC, once GPMI NAND set clock rate for EDO5 mode can cause system
> > hang due to pll2_bus rate changed.
>
> Thanks a lot for your patch.
>
> This fixes the kernel hang issue on a custom imx6sx board with NAND without the
> need of using the workaround found in the NXP kernel:
>
> https://source.codeaurora.org/external/imx/linux-imx/commit/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c?h=lf-5.15.y&id=d03eb99c393f8732f70a1d7d29a3b9c42cccbe48
>
> Tested-by: Fabio Estevam <festevam at denx.de>

Just noticed the build error. I manually applied it to 5.15, so that's
why I didn't notice the problem
with your original patch. It is missing the closing parenthesis:


--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -280,13 +280,13 @@ static void __init imx6sx_clocks_init(struct
device_node *ccm_node)
        hws[IMX6SX_CLK_SSI3_SEL]           =
imx_clk_hw_mux("ssi3_sel",         base + 0x1c,  14,     2,
ssi_sels,          ARRAY_SIZE(ssi_sels));
        hws[IMX6SX_CLK_SSI2_SEL]           =
imx_clk_hw_mux("ssi2_sel",         base + 0x1c,  12,     2,
ssi_sels,          ARRAY_SIZE(ssi_sels));
        hws[IMX6SX_CLK_SSI1_SEL]           =
imx_clk_hw_mux("ssi1_sel",         base + 0x1c,  10,     2,
ssi_sels,          ARRAY_SIZE(ssi_sels));
-       hws[IMX6SX_CLK_QSPI1_SEL]          =
imx_clk_hw_mux_flags("qspi1_sel", base + 0x1c,  7, 3, qspi1_sels,
ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT);
+       hws[IMX6SX_CLK_QSPI1_SEL]          =
imx_clk_hw_mux("qspi1_sel", base + 0x1c,  7, 3, qspi1_sels,
ARRAY_SIZE(qspi1_sels));
        hws[IMX6SX_CLK_PERCLK_SEL]         =
imx_clk_hw_mux("perclk_sel",       base + 0x1c,  6,      1,
perclk_sels,       ARRAY_SIZE(perclk_sels));
        hws[IMX6SX_CLK_VID_SEL]            = imx_clk_hw_mux("vid_sel",
         base + 0x20,  21,     3,      vid_sels,
ARRAY_SIZE(vid_sels));
        hws[IMX6SX_CLK_ESAI_SEL]           =
imx_clk_hw_mux("esai_sel",         base + 0x20,  19,     2,
audio_sels,        ARRAY_SIZE(audio_sels));
        hws[IMX6SX_CLK_CAN_SEL]            = imx_clk_hw_mux("can_sel",
         base + 0x20,  8,      2,      can_sels,
ARRAY_SIZE(can_sels));
        hws[IMX6SX_CLK_UART_SEL]           =
imx_clk_hw_mux("uart_sel",         base + 0x24,  6,      1,
uart_sels,         ARRAY_SIZE(uart_sels));
-       hws[IMX6SX_CLK_QSPI2_SEL]          =
imx_clk_hw_mux_flags("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels,
ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT);
+       hws[IMX6SX_CLK_QSPI2_SEL]          =
imx_clk_hw_mux("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels,
ARRAY_SIZE(qspi2_sels));
        hws[IMX6SX_CLK_SPDIF_SEL]          =
imx_clk_hw_mux("spdif_sel",        base + 0x30,  20,     2,
audio_sels,        ARRAY_SIZE(audio_sels));
        hws[IMX6SX_CLK_AUDIO_SEL]          =
imx_clk_hw_mux("audio_sel",        base + 0x30,  7,      2,
audio_sels,        ARRAY_SIZE(audio_sels));
        hws[IMX6SX_CLK_ENET_PRE_SEL]       =
imx_clk_hw_mux("enet_pre_sel",     base + 0x34,  15,     3,
enet_pre_sels,     ARRAY_SIZE(enet_pre_sels));