[PATCH 1/4] arm64: dts: mt8195: Add dp-intf nodes
AngeloGioacchino Del Regno
angelogioacchino.delregno at collabora.com
Thu Sep 15 01:13:54 PDT 2022
Il 15/09/22 09:58, Bo-Chen Chen ha scritto:
> Add dp-intf0 and dp-intf1 nodes for MT8195.
>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen at mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..93e6a106a9b8 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -2155,5 +2155,28 @@
> clock-names = "apb", "smi", "gals";
> power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> };
> +
> + dp_intf0: dp-intf at 1c015000 {
Please keep the devicetree nodes ordered by mmio.
dp_intf0 goes between mutex at 1c016000 and larb at 1c018000.
> + status = "disabled";
status = "disabled" across the entire mt8195.dtsi nodes is always at the end.
Please keep consistency.
> + compatible = "mediatek,mt8195-dp-intf";
> + reg = <0 0x1c015000 0 0x1000>;
> + interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
> + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
> + <&apmixedsys CLK_APMIXED_TVDPLL1>;
> + clock-names = "engine", "pixel", "pll";
> + };
> +
> + dp_intf1: dp-intf at 1c113000 {
> + compatible = "mediatek,mt8195-dp-intf";
> + reg = <0 0x1c113000 0 0x1000>;
> + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
> + <&vdosys1 CLK_VDO1_DPINTF>,
> + <&apmixedsys CLK_APMIXED_TVDPLL2>;
> + clock-names = "engine", "pixel", "pll";
> + status = "disabled";
> + };
> };
> };
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