[PATCH v2 16/19] EDAC/synopsys: Detach Zynq DDRC controller support
kernel test robot
lkp at intel.com
Sat Sep 10 18:03:30 PDT 2022
Hi Serge,
I love your patch! Perhaps something to improve:
[auto build test WARNING on ras/edac-for-next]
[also build test WARNING on krzk-mem-ctrl/for-next linus/master]
[cannot apply to xilinx-xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Serge-Semin/EDAC-mc-synopsys-Various-fixes-and-cleanups/20220911-034806
base: https://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac-for-next
config: arm-allyesconfig (https://download.01.org/0day-ci/archive/20220911/202209110838.nMRJWlc2-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/f9c107260e46195172faf58ccea98f7de56eae08
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Serge-Semin/EDAC-mc-synopsys-Various-fixes-and-cleanups/20220911-034806
git checkout f9c107260e46195172faf58ccea98f7de56eae08
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/edac/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp at intel.com>
All warnings (new ones prefixed by >>):
drivers/edac/zynq_edac.c: In function 'zynq_mc_init':
>> drivers/edac/zynq_edac.c:378:32: warning: variable 'priv' set but not used [-Wunused-but-set-variable]
378 | struct zynq_edac_priv *priv;
| ^~~~
--
>> drivers/edac/zynq_edac.c:194: warning: expecting prototype for handle_error(). Prototype was for zynq_handle_error() instead
>> drivers/edac/zynq_edac.c:233: warning: expecting prototype for check_errors(). Prototype was for zynq_check_errors() instead
vim +/priv +378 drivers/edac/zynq_edac.c
185
186 /**
187 * handle_error - Handle Correctable and Uncorrectable errors.
188 * @mci: EDAC memory controller instance.
189 * @p: Zynq ECC status structure.
190 *
191 * Handles ECC correctable and uncorrectable errors.
192 */
193 static void zynq_handle_error(struct mem_ctl_info *mci, struct zynq_ecc_status *p)
> 194 {
195 struct zynq_edac_priv *priv = mci->pvt_info;
196 struct zynq_ecc_error_info *pinf;
197
198 if (p->ce_cnt) {
199 pinf = &p->ceinfo;
200
201 snprintf(priv->message, ZYNQ_EDAC_MSG_SIZE,
202 "Row %d Bank %d Col %d Bit %d Data 0x%08x",
203 pinf->row, pinf->bank, pinf->col,
204 pinf->bitpos, pinf->data);
205
206 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
207 p->ce_cnt, 0, 0, 0, 0, 0, -1,
208 priv->message, "");
209 }
210
211 if (p->ue_cnt) {
212 pinf = &p->ueinfo;
213
214 snprintf(priv->message, ZYNQ_EDAC_MSG_SIZE,
215 "Row %d Bank %d Col %d",
216 pinf->row, pinf->bank, pinf->col);
217
218 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
219 p->ue_cnt, 0, 0, 0, 0, 0, -1,
220 priv->message, "");
221 }
222
223 memset(p, 0, sizeof(*p));
224 }
225
226 /**
227 * check_errors - Check controller for ECC errors.
228 * @mci: EDAC memory controller instance.
229 *
230 * Check and post ECC errors. Called by the polling thread.
231 */
232 static void zynq_check_errors(struct mem_ctl_info *mci)
> 233 {
234 struct zynq_edac_priv *priv = mci->pvt_info;
235 int status;
236
237 status = zynq_get_error_info(priv);
238 if (status)
239 return;
240
241 zynq_handle_error(mci, &priv->stat);
242 }
243
244 /**
245 * zynq_get_dtype - Return the controller memory width.
246 * @base: DDR memory controller base address.
247 *
248 * Get the EDAC device type width appropriate for the current controller
249 * configuration.
250 *
251 * Return: a device type width enumeration.
252 */
253 static enum dev_type zynq_get_dtype(const void __iomem *base)
254 {
255 enum dev_type dt;
256 u32 width;
257
258 width = readl(base + ZYNQ_CTRL_OFST);
259 width = (width & ZYNQ_CTRL_BW_MASK) >> ZYNQ_CTRL_BW_SHIFT;
260
261 switch (width) {
262 case ZYNQ_DDRCTL_WDTH_16:
263 dt = DEV_X2;
264 break;
265 case ZYNQ_DDRCTL_WDTH_32:
266 dt = DEV_X4;
267 break;
268 default:
269 dt = DEV_UNKNOWN;
270 }
271
272 return dt;
273 }
274
275 /**
276 * zynq_get_ecc_state - Return the controller ECC enable/disable status.
277 * @base: DDR memory controller base address.
278 *
279 * Get the ECC enable/disable status of the controller.
280 *
281 * Return: true if enabled, otherwise false.
282 */
283 static bool zynq_get_ecc_state(void __iomem *base)
284 {
285 enum dev_type dt;
286 u32 ecctype;
287
288 dt = zynq_get_dtype(base);
289 if (dt == DEV_UNKNOWN)
290 return false;
291
292 ecctype = readl(base + ZYNQ_SCRUB_OFST) & ZYNQ_SCRUB_MODE_MASK;
293 if ((ecctype == ZYNQ_SCRUB_MODE_SECDED) && (dt == DEV_X2))
294 return true;
295
296 return false;
297 }
298
299 /**
300 * zynq_get_memsize - Read the size of the attached memory device.
301 *
302 * Return: the memory size in bytes.
303 */
304 static u32 zynq_get_memsize(void)
305 {
306 struct sysinfo inf;
307
308 si_meminfo(&inf);
309
310 return inf.totalram * inf.mem_unit;
311 }
312
313 /**
314 * zynq_get_mtype - Return the controller memory type.
315 * @base: Zynq ECC status structure.
316 *
317 * Get the EDAC memory type appropriate for the current controller
318 * configuration.
319 *
320 * Return: a memory type enumeration.
321 */
322 static enum mem_type zynq_get_mtype(const void __iomem *base)
323 {
324 enum mem_type mt;
325 u32 memtype;
326
327 memtype = readl(base + ZYNQ_T_ZQ_OFST);
328
329 if (memtype & ZYNQ_T_ZQ_DDRMODE_MASK)
330 mt = MEM_DDR3;
331 else
332 mt = MEM_DDR2;
333
334 return mt;
335 }
336
337 /**
338 * zynq_init_csrows - Initialize the csrow data.
339 * @mci: EDAC memory controller instance.
340 *
341 * Initialize the chip select rows associated with the EDAC memory
342 * controller instance.
343 */
344 static void zynq_init_csrows(struct mem_ctl_info *mci)
345 {
346 struct zynq_edac_priv *priv = mci->pvt_info;
347 struct csrow_info *csi;
348 struct dimm_info *dimm;
349 u32 size, row;
350 int j;
351
352 for (row = 0; row < mci->nr_csrows; row++) {
353 csi = mci->csrows[row];
354 size = zynq_get_memsize();
355
356 for (j = 0; j < csi->nr_channels; j++) {
357 dimm = csi->channels[j]->dimm;
358 dimm->edac_mode = EDAC_SECDED;
359 dimm->mtype = zynq_get_mtype(priv->baseaddr);
360 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
361 dimm->grain = ZYNQ_EDAC_ERR_GRAIN;
362 dimm->dtype = zynq_get_dtype(priv->baseaddr);
363 }
364 }
365 }
366
367 /**
368 * zynq_mc_init - Initialize one driver instance.
369 * @mci: EDAC memory controller instance.
370 * @pdev: platform device.
371 *
372 * Perform initialization of the EDAC memory controller instance and
373 * related driver-private data associated with the memory controller the
374 * instance is bound to.
375 */
376 static void zynq_mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
377 {
> 378 struct zynq_edac_priv *priv;
379
380 mci->pdev = &pdev->dev;
381 priv = mci->pvt_info;
382 platform_set_drvdata(pdev, mci);
383
384 /* Initialize controller capabilities and configuration */
385 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2;
386 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
387 mci->scrub_cap = SCRUB_FLAG_HW_SRC;
388 mci->scrub_mode = SCRUB_NONE;
389
390 mci->edac_cap = EDAC_FLAG_SECDED;
391 mci->ctl_name = "zynq_ddr_controller";
392 mci->dev_name = ZYNQ_EDAC_MOD_STRING;
393 mci->mod_name = ZYNQ_EDAC_MOD_VER;
394
395 edac_op_state = EDAC_OPSTATE_POLL;
396 mci->edac_check = zynq_check_errors;
397
398 mci->ctl_page_to_phys = NULL;
399
400 zynq_init_csrows(mci);
401 }
402
--
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https://01.org/lkp
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