[RFC PATCH 7/9] iommu/arm-smmu-qcom: Merge table from arm-smmu-qcom-debug into match data
Sai Prakash Ranjan
quic_saipraka at quicinc.com
Wed Oct 26 20:08:51 PDT 2022
On 10/21/2022 10:25 PM, Dmitry Baryshkov wrote:
> There is little point in having a separate match table in
> arm-smmu-qcom-debug.c. Merge it into the main match data table in
> arm-smmu-qcom.c
>
> Note, this also enables debug support for sm6375 and ACPI-based sc8180x
> systems, since these SoCs are expected to support tlb_sync debug.
>
Nice cleanup,
Reviewed-by: Sai Prakash Ranjan <quic_saipraka at quicinc.com>
Tested-by: Sai Prakash Ranjan <quic_saipraka at quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> ---
> .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 91 -------------------
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 46 +++++++---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 16 +++-
> 3 files changed, 43 insertions(+), 110 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> index 6eed8e67a0ca..74e9ef2fd580 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> @@ -10,16 +10,6 @@
> #include "arm-smmu.h"
> #include "arm-smmu-qcom.h"
>
> -enum qcom_smmu_impl_reg_offset {
> - QCOM_SMMU_TBU_PWR_STATUS,
> - QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
> - QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
> -};
> -
> -struct qcom_smmu_config {
> - const u32 *reg_offset;
> -};
> -
> void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
> {
> int ret;
> @@ -59,84 +49,3 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
> tbu_pwr_status, sync_inv_ack, sync_inv_progress);
> }
> }
> -
> -/* Implementation Defined Register Space 0 register offsets */
> -static const u32 qcom_smmu_impl0_reg_offset[] = {
> - [QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
> - [QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
> - [QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
> -};
> -
> -static const struct qcom_smmu_config qcm2290_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct qcom_smmu_config sc7180_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct qcom_smmu_config sc7280_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct qcom_smmu_config sc8180x_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct qcom_smmu_config sc8280xp_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct qcom_smmu_config sm6125_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct qcom_smmu_config sm6350_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct qcom_smmu_config sm8150_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct qcom_smmu_config sm8250_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct qcom_smmu_config sm8350_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct qcom_smmu_config sm8450_smmu_cfg = {
> - .reg_offset = qcom_smmu_impl0_reg_offset,
> -};
> -
> -static const struct of_device_id __maybe_unused qcom_smmu_impl_debug_match[] = {
> - { .compatible = "qcom,msm8998-smmu-v2" },
> - { .compatible = "qcom,qcm2290-smmu-500", .data = &qcm2290_smmu_cfg },
> - { .compatible = "qcom,sc7180-smmu-500", .data = &sc7180_smmu_cfg },
> - { .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_cfg},
> - { .compatible = "qcom,sc8180x-smmu-500", .data = &sc8180x_smmu_cfg },
> - { .compatible = "qcom,sc8280xp-smmu-500", .data = &sc8280xp_smmu_cfg },
> - { .compatible = "qcom,sdm630-smmu-v2" },
> - { .compatible = "qcom,sdm845-smmu-500" },
> - { .compatible = "qcom,sm6125-smmu-500", .data = &sm6125_smmu_cfg},
> - { .compatible = "qcom,sm6350-smmu-500", .data = &sm6350_smmu_cfg},
> - { .compatible = "qcom,sm8150-smmu-500", .data = &sm8150_smmu_cfg },
> - { .compatible = "qcom,sm8250-smmu-500", .data = &sm8250_smmu_cfg },
> - { .compatible = "qcom,sm8350-smmu-500", .data = &sm8350_smmu_cfg },
> - { .compatible = "qcom,sm8450-smmu-500", .data = &sm8450_smmu_cfg },
> - { }
> -};
> -
> -const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
> -{
> - const struct of_device_id *match;
> - const struct device_node *np = smmu->dev->of_node;
> -
> - match = of_match_node(qcom_smmu_impl_debug_match, np);
> - if (!match)
> - return NULL;
> -
> - return match->data;
> -}
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 75bc770ccf8c..20cbb39cb670 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -430,11 +430,22 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
> return ERR_PTR(-ENOMEM);
>
> qsmmu->smmu.impl = impl;
> - qsmmu->cfg = qcom_smmu_impl_data(smmu);
> + qsmmu->cfg = data->cfg;
>
> return &qsmmu->smmu;
> }
>
> +/* Implementation Defined Register Space 0 register offsets */
> +static const u32 qcom_smmu_impl0_reg_offset[] = {
> + [QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
> + [QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
> + [QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
> +};
> +
> +static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
> + .reg_offset = qcom_smmu_impl0_reg_offset,
> +};
> +
> /*
> * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
> * there are not enough context banks.
> @@ -452,26 +463,33 @@ static const struct qcom_smmu_match_data qcom_smmu_data = {
> static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
> .impl = &sdm845_smmu_500_impl,
> /* No adreno impl, on sdm845 it is handled by separete sdm845-smmu-v2. */
> + /* No debug configuration */
> +};
> +
> +static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
> + .impl = &qcom_smmu_impl,
> + .adreno_impl = &qcom_adreno_smmu_impl,
> + .cfg = &qcom_smmu_impl0_cfg,
> };
>
> static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
> { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
> { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
> - { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
> + { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
> + { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
> + { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
> + { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
> + { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
> { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
> { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
> { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
> - { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_data },
> - { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_data },
> + { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
> + { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
> + { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
> + { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
> + { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
> + { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
> + { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
> { }
> };
>
> @@ -492,7 +510,7 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
> if (np == NULL) {
> /* Match platform for ACPI boot */
> if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
> - return qcom_smmu_create(smmu, &qcom_smmu_data);
> + return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
> }
> #endif
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
> index 424d8d342ce0..593910567b88 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
> @@ -14,20 +14,26 @@ struct qcom_smmu {
> u32 stall_enabled;
> };
>
> +enum qcom_smmu_impl_reg_offset {
> + QCOM_SMMU_TBU_PWR_STATUS,
> + QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
> + QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
> +};
> +
> +struct qcom_smmu_config {
> + const u32 *reg_offset;
> +};
> +
> struct qcom_smmu_match_data {
> + const struct qcom_smmu_config *cfg;
> const struct arm_smmu_impl *impl;
> const struct arm_smmu_impl *adreno_impl;
> };
>
> #ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
> void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);
> -const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu);
> #else
> static inline void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) { }
> -static inline const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
> -{
> - return NULL;
> -}
> #endif
>
> #endif /* _ARM_SMMU_QCOM_H */
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