[PATCH 0/4] dt-bindings: imx: add nvmem property
Peng Fan (OSS)
peng.fan at oss.nxp.com
Wed Mar 23 21:20:20 PDT 2022
From: Peng Fan <peng.fan at nxp.com>
To i.MX SoC, there are many variants, such as i.MX8M Plus which
feature 4 A53, GPU, VPU, SDHC, FLEXCAN, FEC, eQOS and etc.
But i.MX8M Plus has many parts, one part may not have FLEXCAN,
the other part may not have eQOS or GPU.
But we use one device tree to support i.MX8MP including its parts,
then we need update device tree to mark the disabled IP status "disabled".
In NXP U-Boot, we hardcoded node path and runtime update device tree
status in U-Boot according to fuse value. But this method is not
scalable and need encoding all the node paths that needs check.
By introducing nvmem property for each node that needs runtime update
status property accoridng fuse value, we could use one Bootloader
code piece to support all i.MX SoCs.
The drawback is we need nvmem property for all the nodes which maybe
fused out.
Rob:
I only include limited node bindings in this patchset, and not
include device tree patch. Just wanna to see whether you
agree this approach. If you agree, I'll later post device tree
part and other dt-bindings update, such as MU, USB and etc.
Thanks.
Example as below:
flexcan1: can at 308c0000 {
....
nvmem-cells = <&flexcan_disabled>;
nvmem-cell-names = "disabled";
};
flexcan2: can at 308d0000 {
....
nvmem-cells = <&flexcan_disabled>;
nvmem-cell-names = "disabled";
};
ocotp: efuse at 30350000 {
compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
/* For nvmem subnodes */
#address-cells = <1>;
#size-cells = <1>;
m7_disabled: m7 at 10 {
reg = <0x10 4>;
bits = <21 1>;
};
g1_disabled: g1 at 10 {
reg = <0x10 4>;
bits = <24 1>;
};
g2_disabled: g2 at 10 {
reg = <0x10 4>;
bits = <25 1>;
};
can_disabled: can at 10 {
reg = <0x10 4>;
bits = <28 1>;
};
canfd_disabled: canfd at 10 {
reg = <0x10 4>;
bits = <29 1>;
};
vc8000e_disabled: vc8000e at 10 {
reg = <0x10 4>;
bits = <30 1>;
};
isp1_disabled: isp1 at 10 {
reg = <0x14 4>;
bits = <0 1>;
};
isp2_disabled: isp2 at 10 {
reg = <0x14 4>;
bits = <1 1>;
};
dewrap_disabled: dewrap at 10 {
reg = <0x14 4>;
bits = <2 1>;
};
npu_disabled: dewrap at 10 {
reg = <0x14 4>;
bits = <3 1>;
};
dsp_disabled: dewrap at 10 {
reg = <0x14 4>;
bits = <4 1>;
};
asrc_disabled: dewrap at 10 {
reg = <0x14 4>;
bits = <5 1>;
};
gpu2d_disabled: gpu2d at 10 {
reg = <0x14 4>;
bits = <6 1>;
};
gpu3d_disabled: gpu3d at 10 {
reg = <0x14 4>;
bits = <7 1>;
};
usb1_disabled: usb1 at 10 {
reg = <0x14 4>;
bits = <8 1>;
};
usb2_disabled: usb2 at 10 {
reg = <0x14 4>;
bits = <9 1>;
};
pcie1_disabled: pcie1 at 10 {
reg = <0x14 4>;
bits = <11 1>;
};
enet1_disabled: enet1 at 10 {
reg = <0x14 4>;
bits = <13 1>;
};
enet2_disabled: enet2 at 10 {
reg = <0x14 4>;
bits = <14 1>;
};
csi1_disabled: csi1 at 10 {
reg = <0x14 4>;
bits = <15 1>;
};
csi2_disabled: csi1 at 10 {
reg = <0x14 4>;
bits = <16 1>;
};
dsi1_disabled: dsi1 at 10 {
reg = <0x14 4>;
bits = <17 1>;
};
lvds1_disabled: lvds1 at 10 {
reg = <0x14 4>;
bits = <19 1>;
};
lvds2_disabled: lvds1 at 10 {
reg = <0x14 4>;
bits = <19 1>;
};
eth_mac1: mac-address at 90 {
reg = <0x90 6>;
};
eth_mac2: mac-address at 96 {
reg = <0x96 6>;
};
};
Peng Fan (4):
dt-bindings: can: fsl,flexcan: introduce nvmem property
dt-bindings: net: fsl,fec: introduce nvmem property
dt-bindings: mmc: imx-esdhc: introduce nvmem property
dt-bindings: net: imx-dwmac: introduce nvmem property
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 9 +++++++++
.../devicetree/bindings/net/can/fsl,flexcan.yaml | 9 +++++++++
Documentation/devicetree/bindings/net/fsl,fec.yaml | 9 +++++++++
Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml | 9 +++++++++
4 files changed, 36 insertions(+)
--
2.35.1
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