[PATCH v2 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains

[Lucas Stach]

Am Mittwoch, dem 23.03.2022 um 00:02 +0200 schrieb Laurent Pinchart:
> Hi Marek,
> 
> On Tue, Mar 22, 2022 at 10:31:59PM +0100, Marek Vasut wrote:
> > On 3/22/22 20:03, Laurent Pinchart wrote:
> > > Add the power domains related to the MEDIAMIX to the GPC.
> > > 
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> > > ---
> > >   arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++
> > >   1 file changed, 26 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > index b40a5646f205..b440f22e03e5 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -488,6 +488,11 @@ pgc {
> > >   					#address-cells = <1>;
> > >   					#size-cells = <0>;
> > >   
> > > +					pgc_mipi_phy1: power-domain at 0 {
> > > +						#power-domain-cells = <0>;
> > > +						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
> > 
> > Shouldn't there be this here ?
> > 
> > power-domains = <&pgc_mediamix>;
> 
> I recall Lucas telling me it wasn't needed, and was instead handled
> internally in the gpcv2 driver, due to sequencing requirements, but I
> don't recall the details.

It's not handled by the gpcv2 driver, but the blk-ctrl driver. The blk-
ctrl driver handles the sequencing requirements when powering up/down
the "bus" domain, in that case the mediamix domain. In fact there must
not be any direct connection between the domains in the GPC DT
description as that would cause the requirements for clock and reset
propagation to be violated.

Regards,
Lucas

> 
> > > +					};
> > > +
> > >   					pgc_pcie_phy: power-domain at 1 {
> > >   						#power-domain-cells = <0>;
> > >   						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > @@ -530,6 +535,21 @@ pgc_gpu3d: power-domain at 9 {
> > >   						power-domains = <&pgc_gpumix>;
> > >   					};
> > >   
> > > +					pgc_mediamix: power-domain at 10 {
> > > +						#power-domain-cells = <0>;
> > > +						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
> > > +						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > > +							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > > +						assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > > +								  <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > > +						assigned-clock-rates = <500000000>, <200000000>;
> > > +					};
> > > +
> > > +					pgc_mipi_phy2: power-domain at 16 {
> > > +						#power-domain-cells = <0>;
> > > +						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
> > 
> > Here too ?
>