[PATCH v4] ARM: dts: at91: sama7g5: Add crypto nodes

[Nicolas Ferre]

On 08/02/2022 at 11:56, Tudor Ambarus wrote:
> Describe and enable the AES, SHA and TDES crypto IPs. Tested with the
> extra run-time self tests of the registered crypto algorithms.
> 
> Signed-off-by: Tudor Ambarus <tudor.ambarus at microchip.com>
> Reviewed-by: Claudiu Beznea <claudiu.beznea at microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre at microchip.com>
Queued for 5.18.
Best regards,
   Nicolas

> ---
> v4: use the generic "crypto" node name for all the crypto nodes,
> as recommended by the DT specification. Add Claudiu's R-b tag.
> 
> v3: remove explicit status = "okay", as it's already the default case
> when not specified at all.
> 
> v2:
> - add label to the tdes node
> - update commit description and specify testing method
> - put clocks and clock-names properties before dmas and dma-names
>    because the clocks are mandatory, while DMA is optional for TDES and SHA
> 
>   arch/arm/boot/dts/sama7g5.dtsi | 32 ++++++++++++++++++++++++++++++++
>   1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
> index 7972cb8c2562..2453a6901313 100644
> --- a/arch/arm/boot/dts/sama7g5.dtsi
> +++ b/arch/arm/boot/dts/sama7g5.dtsi
> @@ -393,6 +393,27 @@ pit64b1: timer at e1804000 {
>   			clock-names = "pclk", "gclk";
>   		};
>   
> +		aes: crypto at e1810000 {
> +			compatible = "atmel,at91sam9g46-aes";
> +			reg = <0xe1810000 0x100>;
> +			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
> +			clock-names = "aes_clk";
> +			dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
> +			       <&dma0 AT91_XDMAC_DT_PERID(2)>;
> +			dma-names = "tx", "rx";
> +		};
> +
> +		sha: crypto at e1814000 {
> +			compatible = "atmel,at91sam9g46-sha";
> +			reg = <0xe1814000 0x100>;
> +			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
> +			clock-names = "sha_clk";
> +			dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
> +			dma-names = "tx";
> +		};
> +
>   		flx0: flexcom at e1818000 {
>   			compatible = "atmel,sama5d2-flexcom";
>   			reg = <0xe1818000 0x200>;
> @@ -475,6 +496,17 @@ trng: rng at e2010000 {
>   			status = "disabled";
>   		};
>   
> +		tdes: crypto at e2014000 {
> +			compatible = "atmel,at91sam9g46-tdes";
> +			reg = <0xe2014000 0x100>;
> +			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
> +			clock-names = "tdes_clk";
> +			dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
> +			       <&dma0 AT91_XDMAC_DT_PERID(53)>;
> +			dma-names = "tx", "rx";
> +		};
> +
>   		flx4: flexcom at e2018000 {
>   			compatible = "atmel,sama5d2-flexcom";
>   			reg = <0xe2018000 0x200>;


-- 
Nicolas Ferre