[PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
Chun-Kuang Hu
chunkuang.hu at kernel.org
Mon Feb 7 15:07:32 PST 2022
OK, it seems no one has comment on this patch, so
applied to mediatek-drm-next [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
Chun-Kuang Hu <chunkuang.hu at kernel.org> 於 2022年1月27日 週四 下午11:46寫道：
>
> Hi, Rob:
>
> This patch looks good to me, how do you think about it?
>
> Regards,
> Chun-Kuang.
>
> jason-jh.lin <jason-jh.lin at mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
> >
> > 1. Remove mediatek,dislpay.txt
> > 2. Split each display function block to individual yaml file.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin at mediatek.com>
> > Acked-by: Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > ---
> > .../display/mediatek/mediatek,aal.yaml | 76 ++++++
> > .../display/mediatek/mediatek,ccorr.yaml | 71 ++++++
> > .../display/mediatek/mediatek,color.yaml | 85 +++++++
> > .../display/mediatek/mediatek,disp.txt | 219 ------------------
> > .../display/mediatek/mediatek,dither.yaml | 75 ++++++
> > .../display/mediatek/mediatek,gamma.yaml | 76 ++++++
> > .../display/mediatek/mediatek,merge.yaml | 66 ++++++
> > .../display/mediatek/mediatek,mutex.yaml | 82 +++++++
> > .../display/mediatek/mediatek,od.yaml | 53 +++++
> > .../display/mediatek/mediatek,ovl-2l.yaml | 88 +++++++
> > .../display/mediatek/mediatek,ovl.yaml | 98 ++++++++
> > .../display/mediatek/mediatek,postmask.yaml | 69 ++++++
> > .../display/mediatek/mediatek,rdma.yaml | 115 +++++++++
> > .../display/mediatek/mediatek,split.yaml | 58 +++++
> > .../display/mediatek/mediatek,ufoe.yaml | 61 +++++
> > .../display/mediatek/mediatek,wdma.yaml | 86 +++++++
> > 16 files changed, 1159 insertions(+), 219 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> > delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> > new file mode 100644
> > index 000000000000..044331f5aacb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> > @@ -0,0 +1,76 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display adaptive ambient light processor
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display adaptive ambient light processor, namely AAL,
> > + is responsible for backlight power saving and sunlight visibility improving.
> > + AAL device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8173-disp-aal
> > + - items:
> > + - enum:
> > + - mediatek,mt2712-disp-aal
> > + - mediatek,mt8183-disp-aal
> > + - mediatek,mt8192-disp-aal
> > + - enum:
> > + - mediatek,mt8173-disp-aal
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: AAL Clock
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + aal at 14015000 {
> > + compatible = "mediatek,mt8173-disp-aal";
> > + reg = <0 0x14015000 0 0x1000>;
> > + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&mmsys CLK_MM_DISP_AAL>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> > new file mode 100644
> > index 000000000000..ea45b40edee7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> > @@ -0,0 +1,71 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display color correction
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display color correction, namely CCORR, reproduces correct color
> > + on panels with different color gamut.
> > + CCORR device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8183-disp-ccorr
> > + - items:
> > + - const: mediatek,mt8192-disp-ccorr
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: CCORR Clock
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + ccorr0: ccorr at 1400f000 {
> > + compatible = "mediatek,mt8183-disp-ccorr";
> > + reg = <0 0x1400f000 0 0x1000>;
> > + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> > new file mode 100644
> > index 000000000000..13628f346718
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> > @@ -0,0 +1,85 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display color processor
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display color processor, namely COLOR, provides hue, luma and
> > + saturation adjustments to get better picture quality and to have one panel
> > + resemble the other in their output characteristics.
> > + COLOR device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt2701-disp-color
> > + - items:
> > + - const: mediatek,mt8167-disp-color
> > + - items:
> > + - const: mediatek,mt8173-disp-color
> > + - items:
> > + - enum:
> > + - mediatek,mt7623-disp-color
> > + - mediatek,mt2712-disp-color
> > + - enum:
> > + - mediatek,mt2701-disp-color
> > + - items:
> > + - enum:
> > + - mediatek,mt8183-disp-color
> > + - mediatek,mt8192-disp-color
> > + - enum:
> > + - mediatek,mt8173-disp-color
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: COLOR Clock
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + color0: color at 14013000 {
> > + compatible = "mediatek,mt8173-disp-color";
> > + reg = <0 0x14013000 0 0x1000>;
> > + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > deleted file mode 100644
> > index 78044c340e20..000000000000
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > +++ /dev/null
> > @@ -1,219 +0,0 @@
> > -Mediatek display subsystem
> > -==========================
> > -
> > -The Mediatek display subsystem consists of various DISP function blocks in the
> > -MMSYS register space. The connections between them can be configured by output
> > -and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
> > -of frame signal are distributed to the other function blocks by a DISP_MUTEX
> > -function block.
> > -
> > -All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
> > -For a description of the MMSYS_CONFIG binding, see
> > -Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
> > -
> > -DISP function blocks
> > -====================
> > -
> > -A display stream starts at a source function block that reads pixel data from
> > -memory and ends with a sink function block that drives pixels on a display
> > -interface, or writes pixels back to memory. All DISP function blocks have
> > -their own register space, interrupt, and clock gate. The blocks that can
> > -access memory additionally have to list the IOMMU and local arbiter they are
> > -connected to.
> > -
> > -For a description of the display interface sink function blocks, see
> > -Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
> > -Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
> > -
> > -Required properties (all function blocks):
> > -- compatible: "mediatek,<chip>-disp-<function>", one of
> > - "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
> > - "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
> > - "mediatek,<chip>-disp-rdma" - read DMA / line buffer
> > - "mediatek,<chip>-disp-wdma" - write DMA
> > - "mediatek,<chip>-disp-ccorr" - color correction
> > - "mediatek,<chip>-disp-color" - color processor
> > - "mediatek,<chip>-disp-dither" - dither
> > - "mediatek,<chip>-disp-aal" - adaptive ambient light controller
> > - "mediatek,<chip>-disp-gamma" - gamma correction
> > - "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
> > - "mediatek,<chip>-disp-postmask" - control round corner for display frame
> > - "mediatek,<chip>-disp-split" - split stream to two encoders
> > - "mediatek,<chip>-disp-ufoe" - data compression engine
> > - "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
> > - "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
> > - "mediatek,<chip>-disp-mutex" - display mutex
> > - "mediatek,<chip>-disp-od" - overdrive
> > - the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
> > -- reg: Physical base address and length of the function block register space
> > -- interrupts: The interrupt signal from the function block (required, except for
> > - merge and split function blocks).
> > -- clocks: device clocks
> > - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> > - For most function blocks this is just a single clock input. Only the DSI and
> > - DPI controller nodes have multiple clock inputs. These are documented in
> > - mediatek,dsi.txt and mediatek,dpi.txt, respectively.
> > - An exception is that the mt8183 mutex is always free running with no clocks property.
> > -
> > -Required properties (DMA function blocks):
> > -- compatible: Should be one of
> > - "mediatek,<chip>-disp-ovl"
> > - "mediatek,<chip>-disp-rdma"
> > - "mediatek,<chip>-disp-wdma"
> > - the supported chips are mt2701, mt8167 and mt8173.
> > -- larb: Should contain a phandle pointing to the local arbiter device as defined
> > - in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> > -- iommus: Should point to the respective IOMMU block with master port as
> > - argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > - for details.
> > -
> > -Optional properties (RDMA function blocks):
> > -- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
> > - property to the corresponding rdma
> > - the value is the Max value which defined in hardware data sheet.
> > - mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
> > - mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
> > - mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
> > -
> > -Examples:
> > -
> > -mmsys: clock-controller at 14000000 {
> > - compatible = "mediatek,mt8173-mmsys", "syscon";
> > - reg = <0 0x14000000 0 0x1000>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - #clock-cells = <1>;
> > -};
> > -
> > -ovl0: ovl at 1400c000 {
> > - compatible = "mediatek,mt8173-disp-ovl";
> > - reg = <0 0x1400c000 0 0x1000>;
> > - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > - iommus = <&iommu M4U_PORT_DISP_OVL0>;
> > - mediatek,larb = <&larb0>;
> > -};
> > -
> > -ovl1: ovl at 1400d000 {
> > - compatible = "mediatek,mt8173-disp-ovl";
> > - reg = <0 0x1400d000 0 0x1000>;
> > - interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_OVL1>;
> > - iommus = <&iommu M4U_PORT_DISP_OVL1>;
> > - mediatek,larb = <&larb4>;
> > -};
> > -
> > -rdma0: rdma at 1400e000 {
> > - compatible = "mediatek,mt8173-disp-rdma";
> > - reg = <0 0x1400e000 0 0x1000>;
> > - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > - iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> > - mediatek,larb = <&larb0>;
> > - mediatek,rdma-fifosize = <8192>;
> > -};
> > -
> > -rdma1: rdma at 1400f000 {
> > - compatible = "mediatek,mt8173-disp-rdma";
> > - reg = <0 0x1400f000 0 0x1000>;
> > - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> > - iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> > - mediatek,larb = <&larb4>;
> > -};
> > -
> > -rdma2: rdma at 14010000 {
> > - compatible = "mediatek,mt8173-disp-rdma";
> > - reg = <0 0x14010000 0 0x1000>;
> > - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> > - iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> > - mediatek,larb = <&larb4>;
> > -};
> > -
> > -wdma0: wdma at 14011000 {
> > - compatible = "mediatek,mt8173-disp-wdma";
> > - reg = <0 0x14011000 0 0x1000>;
> > - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> > - iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> > - mediatek,larb = <&larb0>;
> > -};
> > -
> > -wdma1: wdma at 14012000 {
> > - compatible = "mediatek,mt8173-disp-wdma";
> > - reg = <0 0x14012000 0 0x1000>;
> > - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> > - iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> > - mediatek,larb = <&larb4>;
> > -};
> > -
> > -color0: color at 14013000 {
> > - compatible = "mediatek,mt8173-disp-color";
> > - reg = <0 0x14013000 0 0x1000>;
> > - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > -};
> > -
> > -color1: color at 14014000 {
> > - compatible = "mediatek,mt8173-disp-color";
> > - reg = <0 0x14014000 0 0x1000>;
> > - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> > -};
> > -
> > -aal at 14015000 {
> > - compatible = "mediatek,mt8173-disp-aal";
> > - reg = <0 0x14015000 0 0x1000>;
> > - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_AAL>;
> > -};
> > -
> > -gamma at 14016000 {
> > - compatible = "mediatek,mt8173-disp-gamma";
> > - reg = <0 0x14016000 0 0x1000>;
> > - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> > -};
> > -
> > -ufoe at 1401a000 {
> > - compatible = "mediatek,mt8173-disp-ufoe";
> > - reg = <0 0x1401a000 0 0x1000>;
> > - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_UFOE>;
> > -};
> > -
> > -dsi0: dsi at 1401b000 {
> > - /* See mediatek,dsi.txt for details */
> > -};
> > -
> > -dpi0: dpi at 1401d000 {
> > - /* See mediatek,dpi.txt for details */
> > -};
> > -
> > -mutex: mutex at 14020000 {
> > - compatible = "mediatek,mt8173-disp-mutex";
> > - reg = <0 0x14020000 0 0x1000>;
> > - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_MUTEX_32K>;
> > -};
> > -
> > -od at 14023000 {
> > - compatible = "mediatek,mt8173-disp-od";
> > - reg = <0 0x14023000 0 0x1000>;
> > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > - clocks = <&mmsys CLK_MM_DISP_OD>;
> > -};
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> > new file mode 100644
> > index 000000000000..2c05e3019c75
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> > @@ -0,0 +1,75 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display dither processor
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display dither processor, namely DITHER, works by approximating
> > + unavailable colors with available colors and by mixing and matching available
> > + colors to mimic unavailable ones.
> > + DITHER device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8183-disp-dither
> > + - items:
> > + - enum:
> > + - mediatek,mt8192-disp-dither
> > + - enum:
> > + - mediatek,mt8183-disp-dither
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: DITHER Clock
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + dither0: dither at 14012000 {
> > + compatible = "mediatek,mt8183-disp-dither";
> > + reg = <0 0x14012000 0 0x1000>;
> > + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> > new file mode 100644
> > index 000000000000..89ccb8dbadd7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> > @@ -0,0 +1,76 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display gamma correction
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display gamma correction, namely GAMMA, provides a nonlinear
> > + operation used to adjust luminance in display system.
> > + GAMMA device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8173-disp-gamma
> > + - items:
> > + - const: mediatek,mt8183-disp-gamma
> > + - items:
> > + - enum:
> > + - mediatek,mt8192-disp-gamma
> > + - enum:
> > + - mediatek,mt8183-disp-gamma
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: GAMMA Clock
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + gamma at 14016000 {
> > + compatible = "mediatek,mt8173-disp-gamma";
> > + reg = <0 0x14016000 0 0x1000>;
> > + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> > new file mode 100644
> > index 000000000000..7aa6974d509d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> > @@ -0,0 +1,66 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display merge
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display merge, namely MERGE, is used to merge two slice-per-line
> > + inputs into one side-by-side output.
> > + MERGE device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8173-disp-merge
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: MERGE Clock
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + merge at 14017000 {
> > + compatible = "mediatek,mt8173-disp-merge";
> > + reg = <0 0x14017000 0 0x1000>;
> > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&mmsys CLK_MM_DISP_MERGE>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> > new file mode 100644
> > index 000000000000..90f11e12a55e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> > @@ -0,0 +1,82 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display mutex
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek mutex, namely MUTEX, is used to send the triggers signals called
> > + Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
> > + data path or MDP data path.
> > + In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
> > + the shadow register.
> > + MUTEX device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt2701-disp-mutex
> > + - items:
> > + - const: mediatek,mt2712-disp-mutex
> > + - items:
> > + - const: mediatek,mt8167-disp-mutex
> > + - items:
> > + - const: mediatek,mt8173-disp-mutex
> > + - items:
> > + - const: mediatek,mt8183-disp-mutex
> > + - items:
> > + - const: mediatek,mt8192-disp-mutex
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: MUTEX Clock
> > +
> > + mediatek,gce-events:
> > + description:
> > + The event id which is mapping to the specific hardware event signal
> > + to gce. The event id is defined in the gce header
> > + include/dt-bindings/gce/<chip>-gce.h of each chips.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + mutex: mutex at 14020000 {
> > + compatible = "mediatek,mt8173-disp-mutex";
> > + reg = <0 0x14020000 0 0x1000>;
> > + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&mmsys CLK_MM_MUTEX_32K>;
> > + mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> > + <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> > new file mode 100644
> > index 000000000000..7519db315217
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> > @@ -0,0 +1,53 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display overdirve
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display overdrive, namely OD, increases the transition values
> > + of pixels between consecutive frames to make LCD rotate faster.
> > + OD device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt2712-disp-od
> > + - items:
> > + - const: mediatek,mt8173-disp-od
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: OD Clock
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + od at 14023000 {
> > + compatible = "mediatek,mt8173-disp-od";
> > + reg = <0 0x14023000 0 0x1000>;
> > + clocks = <&mmsys CLK_MM_DISP_OD>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> > new file mode 100644
> > index 000000000000..611a2dbdefa4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> > @@ -0,0 +1,88 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display overlay 2 layer
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
> > + for OVL.
> > + OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8183-disp-ovl-2l
> > + - items:
> > + - const: mediatek,mt8192-disp-ovl-2l
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: OVL-2L Clock
> > +
> > + iommus:
> > + description:
> > + This property should point to the respective IOMMU block with master port as argument,
> > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > + mediatek,larb:
> > + description:
> > + This property should contain a phandle pointing to the local arbiter devices defined in
> > + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > + It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + minItems: 1
> > + maxItems: 32
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > + - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + ovl_2l0: ovl at 14009000 {
> > + compatible = "mediatek,mt8183-disp-ovl-2l";
> > + reg = <0 0x14009000 0 0x1000>;
> > + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > + iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
> > + mediatek,larb = <&larb0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> > new file mode 100644
> > index 000000000000..8e4a62cb9c81
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> > @@ -0,0 +1,98 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display overlay
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display overlay, namely OVL, can do alpha blending from
> > + the memory.
> > + OVL device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt2701-disp-ovl
> > + - items:
> > + - const: mediatek,mt8173-disp-ovl
> > + - items:
> > + - const: mediatek,mt8183-disp-ovl
> > + - items:
> > + - const: mediatek,mt8192-disp-ovl
> > + - items:
> > + - enum:
> > + - mediatek,mt7623-disp-ovl
> > + - mediatek,mt2712-disp-ovl
> > + - enum:
> > + - mediatek,mt2701-disp-ovl
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: OVL Clock
> > +
> > + iommus:
> > + description:
> > + This property should point to the respective IOMMU block with master port as argument,
> > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > + mediatek,larb:
> > + description:
> > + This property should contain a phandle pointing to the local arbiter devices defined in
> > + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > + It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + minItems: 1
> > + maxItems: 32
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > + - iommu
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + ovl0: ovl at 1400c000 {
> > + compatible = "mediatek,mt8173-disp-ovl";
> > + reg = <0 0x1400c000 0 0x1000>;
> > + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > + iommus = <&iommu M4U_PORT_DISP_OVL0>;
> > + mediatek,larb = <&larb0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> > new file mode 100644
> > index 000000000000..6ac1da2e8871
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> > @@ -0,0 +1,69 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display postmask
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display postmask, namely POSTMASK, provides round corner pattern
> > + generation.
> > + POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8192-disp-postmask
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: POSTMASK Clock
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + postmask0: postmask at 1400d000 {
> > + compatible = "mediatek,mt8192-disp-postmask";
> > + reg = <0 0x1400d000 0 0x1000>;
> > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> > new file mode 100644
> > index 000000000000..a3c5f4c9fbcd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> > @@ -0,0 +1,115 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek Read Direct Memory Access
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek Read Direct Memory Access(RDMA) component used to read the
> > + data into DMA. It provides real time data to the back-end panel
> > + driver, such as DSI, DPI and DP_INTF.
> > + It contains one line buffer to store the sufficient pixel data.
> > + RDMA device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt2701-disp-rdma
> > + - items:
> > + - const: mediatek,mt8173-disp-rdma
> > + - items:
> > + - const: mediatek,mt8183-disp-rdma
> > + - items:
> > + - enum:
> > + - mediatek,mt7623-disp-rdma
> > + - mediatek,mt2712-disp-rdma
> > + - enum:
> > + - mediatek,mt2701-disp-rdma
> > + - items:
> > + - enum:
> > + - mediatek,mt8192-disp-rdma
> > + - enum:
> > + - mediatek,mt8183-disp-rdma
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: RDMA Clock
> > +
> > + iommus:
> > + description:
> > + This property should point to the respective IOMMU block with master port as argument,
> > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > + mediatek,larb:
> > + description:
> > + This property should contain a phandle pointing to the local arbiter devices defined in
> > + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > + It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + minItems: 1
> > + maxItems: 32
> > +
> > + mediatek,rdma-fifo-size:
> > + description:
> > + rdma fifo size may be different even in same SOC, add this property to the
> > + corresponding rdma.
> > + The value below is the Max value which defined in hardware data sheet
> > + mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
> > + mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
> > + mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [8192, 5120, 2048]
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > + - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + rdma0: rdma at 1400e000 {
> > + compatible = "mediatek,mt8173-disp-rdma";
> > + reg = <0 0x1400e000 0 0x1000>;
> > + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > + iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> > + mediatek,larb = <&larb0>;
> > + mediatek,rdma-fifosize = <8192>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > new file mode 100644
> > index 000000000000..4f08e89c1067
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display split
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display split, namely SPLIT, is used to split stream to two
> > + encoders.
> > + SPLIT device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8173-disp-split
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: SPLIT Clock
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + split0: split at 14018000 {
> > + compatible = "mediatek,mt8173-disp-split";
> > + reg = <0 0x14018000 0 0x1000>;
> > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> > new file mode 100644
> > index 000000000000..6e8748529e73
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> > @@ -0,0 +1,61 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display UFOe
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek display UFOe stands for Unified Frame Optimization engine.
> > + UFOe can cut the data rate for DSI port which may lead to reduce power
> > + consumption.
> > + UFOe device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8173-disp-ufoe
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: UFOe Clock
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + ufoe at 1401a000 {
> > + compatible = "mediatek,mt8173-disp-ufoe";
> > + reg = <0 0x1401a000 0 0x1000>;
> > + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&mmsys CLK_MM_DISP_UFOE>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> > new file mode 100644
> > index 000000000000..aaf5649b6413
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> > @@ -0,0 +1,86 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek Write Direct Memory Access
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > + - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description: |
> > + Mediatek Write Direct Memory Access(WDMA) component used to write
> > + the data into DMA.
> > + WDMA device node must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8173-disp-wdma
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > + clocks:
> > + items:
> > + - description: WDMA Clock
> > +
> > + iommus:
> > + description:
> > + This property should point to the respective IOMMU block with master port as argument,
> > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > + mediatek,larb:
> > + description:
> > + This property should contain a phandle pointing to the local arbiter devices defined in
> > + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > + It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + minItems: 1
> > + maxItems: 32
> > +
> > + mediatek,gce-client-reg:
> > + description: The register of client driver can be configured by gce with
> > + 4 arguments defined in this property, such as phandle of gce, subsys id,
> > + register offset and size. Each GCE subsys id is mapping to a client
> > + defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > + - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + wdma0: wdma at 14011000 {
> > + compatible = "mediatek,mt8173-disp-wdma";
> > + reg = <0 0x14011000 0 0x1000>;
> > + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> > + iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> > + mediatek,larb = <&larb0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> > + };
> > --
> > 2.18.0
> >
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