[PATCH] arm64: dts: imx8mp: move PCIe controller clock config to SoC dtsi

[Hongxing Zhu]

> -----Original Message-----
> From: Lucas Stach <l.stach at pengutronix.de>
> Sent: 2022年12月17日 4:00
> To: Shawn Guo <shawnguo at kernel.org>
> Cc: Pengutronix Kernel Team <kernel at pengutronix.de>; dl-linux-imx
> <linux-imx at nxp.com>; tharvey at gateworks.com; devicetree at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org; patchwork-lst at pengutronix.de
> Subject: [PATCH] arm64: dts: imx8mp: move PCIe controller clock config to SoC
> dtsi
> 
> The only difference in PCIe clock configuration between boards is how the PCIe
> reference clock is generated. The refclock configuration is fully contained in
> the PCIe PHY node, so the PCIe controller clocks can be set up in the SoC dtsi,
> as there is no reason for any board to use a different configuration.
> 
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>

Agree.
Reviewed-by: Richard Zhu <hongxing.zhu at nxp.com>

Best Regards
Richard Zhu

> ---
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts           | 7 -------
>  arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 7 -------
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi              | 7 +++++++
>  3 files changed, 7 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index e2e1898d3d12..faed1d179238 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -400,13 +400,6 @@ &pcie {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> -		 <&clk IMX8MP_CLK_PCIE_ROOT>,
> -		 <&clk IMX8MP_CLK_HSIO_AXI>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> -	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> -	assigned-clock-rates = <10000000>;
> -	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
>  	vpcie-supply = <&reg_pcie0>;
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
> b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
> index ceeca4966fc5..007dd85fa086 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
> @@ -593,13 +593,6 @@ &pcie {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> -		 <&clk IMX8MP_CLK_PCIE_ROOT>,
> -		 <&clk IMX8MP_CLK_HSIO_AXI>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> -	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> -	assigned-clock-rates = <10000000>;
> -	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
>  	status = "okay";
>  };
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 7a6e6221f421..4ef36ebc6bfe 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1183,6 +1183,13 @@ pcie: pcie at 33800000 {
>  			compatible = "fsl,imx8mp-pcie";
>  			reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
>  			reg-names = "dbi", "config";
> +			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> +				 <&clk IMX8MP_CLK_PCIE_ROOT>,
> +				 <&clk IMX8MP_CLK_HSIO_AXI>;
> +			clock-names = "pcie", "pcie_aux", "pcie_bus";
> +			assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> +			assigned-clock-rates = <10000000>;
> +			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> --
> 2.30.2