[PATCH V2 1/2] EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR
Sherry Sun
sherry.sun at nxp.com
Wed Apr 20 18:53:12 PDT 2022
V3.X Synopsys EDAC DDR doesn't have the QOS Interrupt register, need
to change to use the ECC Clear Register to disable the interrupts.
Signed-off-by: Sherry Sun <sherry.sun at nxp.com>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta at xilinx.com>
Acked-by: Michal Simek <michal.simek at xilinx.com>
---
Changes in V2:
1. Add the Reviewed-by and Acked-by tag.
---
drivers/edac/synopsys_edac.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 40b1abeca856..88a481043d4c 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -865,8 +865,11 @@ static void enable_intr(struct synps_edac_priv *priv)
static void disable_intr(struct synps_edac_priv *priv)
{
/* Disable UE/CE Interrupts */
- writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
- priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+ if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+ writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+ else
+ writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+ priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
}
static int setup_irq(struct mem_ctl_info *mci,
--
2.17.1
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