[PATCH v2 14/16] arm64: Add a capability for FEAT_ECV

[Will Deacon]

On Wed, Sep 22, 2021 at 10:19:39PM +0100, Marc Zyngier wrote:
> Add a new capability to detect the Enhanced Counter Virtualization
> feature (FEAT_ECV).
> 
> Reviewed-by: Oliver Upton <oupton at google.com>
> Signed-off-by: Marc Zyngier <maz at kernel.org>
> ---
>  arch/arm64/kernel/cpufeature.c | 10 ++++++++++
>  arch/arm64/tools/cpucaps       |  1 +
>  2 files changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index f8a3067d10c6..26b11ce8fff6 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1926,6 +1926,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.sign = FTR_UNSIGNED,
>  		.min_field_value = 1,
>  	},
> +	{
> +		.desc = "Enhanced Counter Virtualization",
> +		.capability = ARM64_HAS_ECV,
> +		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
> +		.matches = has_cpuid_feature,
> +		.sys_reg = SYS_ID_AA64MMFR0_EL1,
> +		.field_pos = ID_AA64MMFR0_ECV_SHIFT,
> +		.sign = FTR_UNSIGNED,
> +		.min_field_value = 1,
> +	},

Could we add a HWCAP for this and change the field to FTR_VISIBLE, please? I
know most users of the counter are indirected via the vDSO, but there are
some users out there using the counter directly and it would save them
having to probe via SIGILL if there was a hwcap available.

Cheers,

Will