[PATCH v3 02/12] KVM: arm64: selftests: Add write_sysreg_s and read_sysreg_s

[Oliver Upton]

On Wed, Sep 01, 2021 at 09:28:28PM +0000, Oliver Upton wrote:
> On Wed, Sep 01, 2021 at 09:14:02PM +0000, Raghavendra Rao Ananta wrote:
> > For register names that are unsupported by the assembler or the ones
> > without architectural names, add the macros write_sysreg_s and
> > read_sysreg_s to support them.
> > 
> > The functionality is derived from kvm-unit-tests and kernel's
> > arch/arm64/include/asm/sysreg.h.
> > 
> > Signed-off-by: Raghavendra Rao Ananta <rananta at google.com>
> 
> Would it be possible to just include <asm/sysreg.h>? See
> tools/arch/arm64/include/asm/sysreg.h

Geez, sorry for the noise. I mistakenly searched from the root of my
repository, not the tools/ directory.

In any case, you could perhaps just drop the kernel header there just to
use the exact same source for kernel and selftest.

Thanks,
Oliver

> > ---
> >  .../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++
> >  1 file changed, 61 insertions(+)
> > 
> > diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h
> > index 3cbaf5c1e26b..082cc97ad8d3 100644
> > --- a/tools/testing/selftests/kvm/include/aarch64/processor.h
> > +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h
> > @@ -118,6 +118,67 @@ void vm_install_exception_handler(struct kvm_vm *vm,
> >  void vm_install_sync_handler(struct kvm_vm *vm,
> >  		int vector, int ec, handler_fn handler);
> >  
> > +/*
> > + * ARMv8 ARM reserves the following encoding for system registers:
> > + * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
> > + *  C5.2, version:ARM DDI 0487A.f)
> > + *	[20-19] : Op0
> > + *	[18-16] : Op1
> > + *	[15-12] : CRn
> > + *	[11-8]  : CRm
> > + *	[7-5]   : Op2
> > + */
> > +#define Op0_shift	19
> > +#define Op0_mask	0x3
> > +#define Op1_shift	16
> > +#define Op1_mask	0x7
> > +#define CRn_shift	12
> > +#define CRn_mask	0xf
> > +#define CRm_shift	8
> > +#define CRm_mask	0xf
> > +#define Op2_shift	5
> > +#define Op2_mask	0x7
> > +
> > +/*
> > + * When accessed from guests, the ARM64_SYS_REG() doesn't work since it
> > + * generates a different encoding for additional KVM processing, and is
> > + * only suitable for userspace to access the register via ioctls.
> > + * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec.
> > + */
> > +#define sys_reg(op0, op1, crn, crm, op2) \
> > +	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
> > +	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
> > +	 ((op2) << Op2_shift))
> > +
> > +asm(
> > +"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
> > +"	.equ	.L__reg_num_x\\num, \\num\n"
> > +"	.endr\n"
> > +"	.equ	.L__reg_num_xzr, 31\n"
> > +"\n"
> > +"	.macro	mrs_s, rt, sreg\n"
> > +"	.inst	0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > +"	.endm\n"
> > +"\n"
> > +"	.macro	msr_s, sreg, rt\n"
> > +"	.inst	0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > +"	.endm\n"
> > +);
> > +
> > +/*
> > + * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg()
> > + */
> > +#define read_sysreg_s(reg) ({						\
> > +	u64 __val;							\
> > +	asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val));	\
> > +	__val;								\
> > +})
> > +
> > +#define write_sysreg_s(reg, val) do {					\
> > +	u64 __val = (u64)val;						\
> > +	asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\
> > +} while (0)
> > +
> >  #define write_sysreg(reg, val)						  \
> >  ({									  \
> >  	u64 __val = (u64)(val);						  \
> > -- 
> > 2.33.0.153.gba50c8fa24-goog
> >