[PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU

[Alexandru Elisei]

Hi Marc,

Tested on FVP and the nasty splat goes away, so it works for me:

Tested-by: Alexandru Elisei <alexandru.elisei at arm.com>

The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on
register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the
bit behave as RES0, which is the architectural value for the field when
FEAT_PMUv3p7 is absent. So the patch looks correct to me:

Reviewed-by: Alexandru Elisei <alexandru.elisei at arm.com>

Thanks,
Alex

On Fri, Nov 26, 2021 at 11:55:33AM +0000, Marc Zyngier wrote:
> When running a KVM guest hosted on an ARMv8.7 machine, the host
> kernel complains that it doesn't know about the architected number
> of events.
> 
> Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.
> 
> Signed-off-by: Marc Zyngier <maz at kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 1 +
>  arch/arm64/kvm/pmu-emul.c       | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index cdb590840b3f..5de90138d0a4 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -1036,6 +1036,7 @@
>  #define ID_AA64DFR0_PMUVER_8_1		0x4
>  #define ID_AA64DFR0_PMUVER_8_4		0x5
>  #define ID_AA64DFR0_PMUVER_8_5		0x6
> +#define ID_AA64DFR0_PMUVER_8_7		0x7
>  #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
>  
>  #define ID_AA64DFR0_PMSVER_8_2		0x1
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index a5e4bbf5e68f..ca92cc5c71c6 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
>  	case ID_AA64DFR0_PMUVER_8_1:
>  	case ID_AA64DFR0_PMUVER_8_4:
>  	case ID_AA64DFR0_PMUVER_8_5:
> +	case ID_AA64DFR0_PMUVER_8_7:
>  		return GENMASK(15, 0);
>  	default:		/* Shouldn't be here, just for sanity */
>  		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
> -- 
> 2.30.2
>