(EXT) Re: [PATCH 1/1] clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites

[Adam Ford]

On Wed, Nov 3, 2021 at 9:33 AM Alexander Stein
<alexander.stein at ew.tq-group.com> wrote:
>
> Am Mittwoch, dem 03.11.2021 um 09:25 -0500 schrieb Adam Ford:
> > On Wed, Nov 3, 2021 at 7:41 AM Alexander Stein
> > <
> > alexander.stein at ew.tq-group.com
> > > wrote:
> > > Only imx8m_clk_hw_composite_core needs to set this flag.
> > >

Tested-by: Adam Ford <aford173 at gmail.com> #imx8mm-beacon

> > > Fixes: a60fe746df94 ("clk: imx: Rework all imx_clk_hw_composite
> > > wrappers")
> > > Signed-off-by: Alexander Stein <
> > > alexander.stein at ew.tq-group.com
> > > >
> > > ---
> > > This is from clk_summary on a imx8mq custom board where you can
> > > clearly
> > > see the before the divider is limited to 8 (core composite)
> > >
> > > before:
> > > video_pll1_out        2        2        0  1031999997          0
> > >   0  50000         Y
> > >    dsi_phy_ref        1        1        0   129000000          0
> > >   0  50000         Y
> > >    lcdif_pixel        2        2        0   129000000          0
> > >   0  50000         Y
> > >
> > > after:
> > > video_pll1_out        2        2        0  1031999997          0
> > >   0  50000         Y
> > >    dsi_phy_ref        1        1        0    24000000          0
> > >   0  50000         Y
> > >    lcdif_pixel        2        2        0    68800000          0
> > >   0  50000         Y
> > >

This appears to fix a couple clocks on the imx8mm as well.

root at beacon-imx8mm-kit:~# diff before.txt after.txt
225c225
<                 dsi_phy_ref           0        0        0
99000000          0     0  50000         N
---
>                 dsi_phy_ref           0        0        0    27000000          0     0  50000         N
234,235c234,235
<                 sai3                  0        0        0
49152000          0     0  50000         N
<                    sai3_root_clk       0        0        0
49152000          0     0  50000         N
---
>                 sai3                  0        0        0    24576000          0     0  50000         N
>                    sai3_root_clk       0        0        0    24576000          0     0  50000         N

At least for sai3 on the beacon board,  24576000 is the desired clock rate.

> > >  drivers/clk/imx/clk.h | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> >
> > I attempted to apply this against linux/master and it doesn't apply.
> > What branch did you use?
>
> The referenced commit a60fe746df94 is not in Linus' tree yet, but in
> linux-next. My patch is based on linux-next/next-20211101. Sorry missed
> to mention that.
>
> Best regards,
> Alexander
>
> > > >
> > > index 819949973db1..7d220a01de1f 100644
> > > --- a/drivers/clk/imx/clk.h
> > > +++ b/drivers/clk/imx/clk.h
> > > @@ -391,11 +391,11 @@ struct clk_hw *__imx8m_clk_hw_composite(const
> > > char *name,
> > >
> > >  #define imx8m_clk_hw_composite(name, parent_names, reg) \
> > >         _imx8m_clk_hw_composite(name, parent_names, reg, \
> > > -                       IMX_COMPOSITE_CORE,
> > > IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
> > > +                       0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
> > >
> > >  #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
> > >         _imx8m_clk_hw_composite(name, parent_names, reg, \
> > > -                       IMX_COMPOSITE_CORE,
> > > IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
> > > +                       0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
> > >
> > >  #define imx8m_clk_hw_composite_bus(name, parent_names, reg)    \
> > >         _imx8m_clk_hw_composite(name, parent_names, reg, \
> > > --
> > > 2.25.1
> > >
>
>