[PATCH V2] clk: imx: gate off peripheral clock slice

[Peng Fan]

> Subject: Re: [PATCH V2] clk: imx: gate off peripheral clock slice
> 
> Hello Peng, Abel,
> 
> On 25.10.21 14:08, Abel Vesa wrote:
> > On 21-10-25 20:29:02, Peng Fan (OSS) wrote:
> >> From: Peng Fan <peng.fan at nxp.com>
> >>
> >> The Peripheral clocks are default enabled when SoC power on, and
> >> bootloader not gate off the clocks when booting Linux Kernel.
> >>
> >> So Linux Kernel is not aware the peripheral clocks are enabled and
> >> still take them as disabled because of enable count is zero.
> >>
> >> Then Peripheral clock's source without clock gated off could be
> >> changed when have assigned-parents in device tree
> >>
> >> However, per i.MX8M* reference mannual, "Peripheral clock slices must
> >> be stopped to change the clock source", so need to gate off the the
> >> peripheral clock when registering the clocks to avoid glitch.
> >>
> >> Tested boot on i.MX8MM/P-EVK board
> 
> I just noticed this breaks earlycon on an i.MX8MN, I assume because the
> earlycon driver will access unclocked registers.
> 
> On the i.MX8MN, I also noticed that disabling usb_phy_ref hangs the system,
> whether via sysfs or via this patch. Still trying to figure that one out.


This patch indeed breaks earlycon, need to think out how to fix this.
But I am still not sure why usb_phy_ref matters here.

Thanks,
Peng.

> 
> Cheers,
> Ahmad
> 
> >> Fixes: d3ff9728134e ("clk: imx: Add imx composite clock")
> >> Signed-off-by: Peng Fan <peng.fan at nxp.com>
> >> ---
> >>
> >> V2:
> >>  Add Fixes tag
> >>
> >>  drivers/clk/imx/clk-composite-8m.c | 9 ++++++++-
> >>  1 file changed, 8 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/clk/imx/clk-composite-8m.c
> >> b/drivers/clk/imx/clk-composite-8m.c
> >> index 2dfd6149e528..ee41fbf90589 100644
> >> --- a/drivers/clk/imx/clk-composite-8m.c
> >> +++ b/drivers/clk/imx/clk-composite-8m.c
> >> @@ -184,6 +184,7 @@ struct clk_hw *__imx8m_clk_hw_composite(const
> char *name,
> >>  	struct clk_mux *mux = NULL;
> >>  	const struct clk_ops *divider_ops;
> >>  	const struct clk_ops *mux_ops;
> >> +	u32 val;
> >>
> >>  	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> >>  	if (!mux)
> >> @@ -216,8 +217,14 @@ struct clk_hw
> *__imx8m_clk_hw_composite(const char *name,
> >>  		div->width = PCG_PREDIV_WIDTH;
> >>  		divider_ops = &imx8m_clk_composite_divider_ops;
> >>  		mux_ops = &clk_mux_ops;
> >> -		if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED))
> >> +		if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED)) {
> >>  			flags |= CLK_SET_PARENT_GATE;
> >> +			if (!(flags & CLK_IS_CRITICAL)) {
> >> +				val = readl(reg);
> >> +				val &= ~BIT(PCG_CGC_SHIFT);
> >> +				writel(val, reg);
> >> +			}
> >> +		}
> >
> > Though I'm usually against special cases like this one. I think the
> > clock core needs some generic flag that would read the state from HW
> > on probe and/or another generic flag for disabling on probe.
> >
> > But for now, I'm OK with this:
> >
> > Reviewed-by: Abel Vesa <abel.vesa at nxp.com>
> >
> >>  	}
> >>
> >>  	div->lock = &imx_ccm_lock;
> >> --
> >> 2.30.0
> >>
> >
> >
> 
> 
> --
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