[PATCH v3 6/8] clk: Add Sunplus SP7021 clock driver
kernel test robot
lkp at intel.com
Mon Nov 1 03:16:33 PDT 2021
Hi Qin,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pza/reset/next]
[also build test WARNING on robh/for-next clk/clk-next tip/irq/core linus/master v5.15 next-20211029]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211101-140155
base: https://git.pengutronix.de/git/pza/linux reset/next
config: openrisc-randconfig-r015-20211101 (attached as .config)
compiler: or1k-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/9767714cf5c22192f99adb0d8e344cb5e38a2e33
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211101-140155
git checkout 9767714cf5c22192f99adb0d8e344cb5e38a2e33
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=openrisc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
All warnings (new ones prefixed by >>):
>> drivers/clk/clk-sp7021.c:663:13: warning: no previous prototype for 'clk_register_sp_pll' [-Wmissing-prototypes]
663 | struct clk *clk_register_sp_pll(const char *name, const char *parent,
| ^~~~~~~~~~~~~~~~~~~
vim +/clk_register_sp_pll +663 drivers/clk/clk-sp7021.c
662
> 663 struct clk *clk_register_sp_pll(const char *name, const char *parent,
664 void __iomem *reg, int pd_bit, int bp_bit,
665 unsigned long brate, int shift, int width,
666 spinlock_t *lock)
667 {
668 struct sp_pll *pll;
669 struct clk *clk;
670 //unsigned long flags = 0;
671 struct clk_init_data initd = {
672 .name = name,
673 .parent_names = &parent,
674 .ops = (bp_bit >= 0) ? &sp_pll_ops : &sp_pll_sub_ops,
675 .num_parents = 1,
676 .flags = CLK_IGNORE_UNUSED
677 };
678
679 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
680 if (!pll)
681 return ERR_PTR(-ENOMEM);
682
683 if (reg == PLLSYS_CTL)
684 initd.flags |= CLK_IS_CRITICAL;
685
686 pll->hw.init = &initd;
687 pll->reg = reg;
688 pll->pd_bit = pd_bit;
689 pll->bp_bit = bp_bit;
690 pll->brate = brate;
691 pll->div_shift = shift;
692 pll->div_width = width;
693 pll->lock = lock;
694
695 clk = clk_register(NULL, &pll->hw);
696 if (WARN_ON(IS_ERR(clk))) {
697 kfree(pll);
698 } else {
699 pr_info("%-20s%lu\n", name, clk_get_rate(clk));
700 clk_register_clkdev(clk, NULL, name);
701 }
702
703 return clk;
704 }
705
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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