[PATCH v2 05/16] arm64: Remove uaccess toggle from __flush_cache_range macro

[Mark Rutland]

On Mon, May 17, 2021 at 08:51:13AM +0100, Fuad Tabba wrote:
> The uaccess toggle isn't part of the cache maintenance operation.
> Move it directly to where it's needed.
> 
> No functional change intended.
> 
> Signed-off-by: Fuad Tabba <tabba at google.com>
> ---
>  arch/arm64/mm/cache.S | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
> index 6babaaf34f17..d74b20cd6449 100644
> --- a/arch/arm64/mm/cache.S
> +++ b/arch/arm64/mm/cache.S
> @@ -26,9 +26,6 @@
>   *	- needs_uaccess - (macro parameter) might access user space memory
>   */
>  .macro	__flush_cache_range, needs_uaccess
> -	.if 	\needs_uaccess
> -	uaccess_ttbr0_enable x2, x3, x4
> -	.endif
>  alternative_if ARM64_HAS_CACHE_IDC
>  	dsb	ishst
>  	b	7f
> @@ -55,9 +52,6 @@ alternative_else_nop_endif
>  	invalidate_icache_by_line x0, x1, x2, x3, \needs_uaccess, 9f
>  8:	mov	x0, #0
>  1:
> -	.if	\needs_uaccess
> -	uaccess_ttbr0_disable x1, x2
> -	.endif
>  	ret
>  
>  	.if 	\needs_uaccess
> @@ -92,7 +86,9 @@ SYM_FUNC_END(__flush_icache_range)
>   *	- end     - virtual end address of region
>   */
>  SYM_FUNC_START(__flush_cache_user_range)
> +	uaccess_ttbr0_enable x2, x3, x4
>  	__flush_cache_range needs_uaccess=1
> +	uaccess_ttbr0_disable x1, x2
>  SYM_FUNC_END(__flush_cache_user_range)

The RET is still in the __flush_cache_range macro, so I don't think
we'll ever execute the uaccess_ttbr0_disable step here.

Mark.

>  
>  /*
> -- 
> 2.31.1.751.gd2f1c929bd-goog
>