About add an A64FX cache control function into resctrl

[tan.shaopeng at fujitsu.com]

Hi Reinette,

> On 4/21/2021 1:37 AM, tan.shaopeng at fujitsu.com wrote:
> > Hi,
> >
> > Ping... any comments&advice about add an A64FX cache control function
> into resctrl?
> 
> My apologies for the delay.
> 
> >
> > Best regards
> > Tan Shaopeng
> >
> >> Hello
> >>
> >>
> >> I'm Tan Shaopeng from Fujitsu Limited.
> >>
> >> I’m trying to implement Fujitsu A64FX’s cache related features.
> >> It is a cache partitioning function we called sector cache function
> >> that using the value of the tag that is upper 8 bits of the 64bit
> >> address and the value of the sector cache register to control virtual cache
> capacity of the L1D&L2 cache.
> >>
> >> A few days ago, when I sent a driver that realizes this function to
> >> ARM64 kernel community, Will Deacon and Arnd Bergmann suggested an
> >> idea to add the sector cache function of A64FX into resctrl.
> >>
> https://lore.kernel.org/linux-arm-kernel/CAK8P3a2pFcNTw9NpRtQfYr7A5Oc
> >> Z=As2kM0D_sbfFcGQ_J2Q+Q at mail.gmail.com/
> >>
> >> Based on my study, I think the sector cache function of A64FX can be
> >> added into the allocation features of resctrl after James' resctrl rework has
> finished.
> >> But, in order to implement this function, more interfaces for resctrl are
> need.
> >> The details are as follow, and could you give me some advice?
> >>
> >> [Sector cache function]
> >> The sector cache function split cache into multiple sectors and
> >> control them separately. It is implemented on the L1D cache and
> >> L2 cache in the A64FX processor and can be controlled individually
> >> for L1D cache and L2 cache. A64FX has no L3 cache. Each L1D cache and
> >> L2 cache has 4 sectors. Which L1D sector is used is specified by the
> >> value of [57:56] bits of address, how many ways of sector are
> >> specified by the value of register (IMP_SCCR_L1_EL0).
> >> Which L2 sector is used is specified by the value of [56] bits of
> >> address, and how many ways of sector are specified by value of
> >> register (IMP_SCCR_ASSIGN_EL1, IMP_SCCR_SET0_L2_EL1,
> >> IMP_SCCR_SET1_L2_EL1).
> >>
> >> For more details of sector cache function, see A64FX HPC extension
> >> specification (1.2. Sector cache) in https://github.com/fujitsu/A64FX
> 
> The overview in section 12 was informative but very high level.
> I was not able to find any instance of "IMP_SCCR" in this document to explore
> how this cache allocation works.

Maybe you have already known, the sector cache works as follows. 
 - Set the maximum number of ways for sector (id = 0/1/2/3) of L1&L2 
   by setting the "IMP_SCCR" register. 
 - When running a task, the sector id is specified by [56:57] bits of 
   the virtual address. If the sector id is not specified, the sector 
   id specified in IMP_SCCR_ASSIGN_EL1.default_sector will be used.

> Are these cache sectors exposed to the OS in any way? For example, when the
> OS discovers the cache, does it learn about these sectors and expose the
> details to user space (/sys/devices/system/cpuX/cache)?

These cache sectors are not exposed to the OS in any way.

> The overview of Sector Cache in that document provides details of how the size
> of the sector itself is dynamically adjusted to usage. That description is quite
> cryptic but it seems like a sector, since the number of ways associated with it
> can dynamically change, is more equivalent to a class of service or resource
> group in the resctrl environment.

I explained the difference between "sector" and "class of service" 
in another email.

> I really may be interpreting things wrong here, could you perhaps point me to
> where I can obtain more details?

I'm sorry, there is no documentation other than the manual and 
specifications. More details about how sector cache function works 
as follows. 
(1) By setting the access control register IMP_SCCR_CTRL_EL1, cache 
    capacity setting registers (IMP_SCCR_CTRL_EL1, IMP_SCCR_ASSIGN_EL1, 
    IMP_SCCR_L1_EL0, IMP_SCCR_SET0_L2_EL1, IMP_SCCR_SET1_L2_EL1, 
    IMP_SCCR_VSCCR_L2_EL0) can be set from user space or kernel space. 
(2) Set L1 sector cache capacity register from kernel space. 
    By setting the register IMP_SCCR_L1_EL0, set the maximum number 
    of ways of sector (id = 0/1/2/3) of L1. 
(3) Set L2 sector cache capacity register. 
    (one of cases) By setting IMP_SCCR_ASSIGN_EL1.assign = 0 from 
    kernel space, IMP_SCCR_VSCCR_L2_EL0 becomes alias of 
    IMP_SCCR_SET0_L2_EL1. By setting IMP_SCCR_VSCCR_L2_EL0 from user 
    space, set the maximum number of ways of sector (id = 0/1) of L2. 
(4) When running a task, the sector ID of L1 is decided by [56:57] 
    bits of virtual address, and the sector ID of L2 is decided by 
    [56] bit of the address. These bits are programed by the users.

> >> [Difference between resctrl(CAT) and this sector cache function]
> >> L2/L3 CAT (Cache Allocation Technology) enables the user to specify
> >> some physical partition of cache space that an application can fill.
> >> A64FX's L1D/L2 cache has 4 sectors and 16ways. This sector function
> >> enables a user to specify number of ways each sector uses.
> >> Therefore, for CAT it is enough to specify a cache portion for each
> >> cache_id (socket). On the other hand, sector cache needs to specify
> >> cache portion of each sector for each cache_id, and following
> >> extension to resctrl interface is needed to support sector cache.
> >>
> >> [Idear for A64FX sector cache function control interface (schemata
> >> file details)]
> >>
> L1:<cache_id0>=<cwbm>,<cwbm>,<cwbm>,<cwbm>;<cache_id1>=<cw
> >> bm>,<cwbm>,<cwbm>,<cwbm>;…
> >>
> L2:<cache_id0>=>=<cwbm>,<cwbm>,<cwbm>,<cwbm>;<cache_id1>=
> >> <cwbm>,<cwbm>,<cwbm>,<cwbm>;…
> >>
> >> ・L1: Add a new interface to control the L1D cache.
> >> ・<cwbm>,<cwbm>,<cwbm>,<cwbm>：Specify the number of ways for
> each
> >> sector.
> >> ・cwbm：Specify the number of ways in each sector as a bitmap
> (percentage),
> >>    but the bitmap does not indicate the location of the cache.
> >> * In the sector cache function, L2 sector cache way setting register is
> >>    shared among PEs (Processor Element) in shared domain. If two PEs
> >>    which share L2 cache belongs to different resource groups, one
> resource
> >>    group's L2 setting will affect to other resource group's L2 setting.
> 
> In resctrl a "resource group" can be viewed as a class of service.

Thanks for your explanation. Adding sector cache function into resctrl, 
I will use this mechanism of resctrl as it is.

> >> * Since A64FX does not support MPAM, it is not necessary to consider
> >>    how to switch between MPAM and sector cache function now.
> >>
> >> Some questions:
> >> 1.I'm still studying about RDT, could you tell me whether RDT has
> >>    the similar mechanism with sector cache function?
> 
> This is not clear to me yet. One thing to keep in mind is that a bit in the capacity
> bitmask could correspond to some number of ways in a cache, but it does not
> have to. It is essentially a hint to hardware on how much cache space needs to
> be allocated while also indicating overlap and isolation from other allocations.
> 
> resctrl already supports the bitmask being interpreted differently between
> architectures and with the MPAM support there will be even more support for
> different interpretations.

when adding sector cache function into resctrl, 
the bitmap will only show the maximum number of ways of sector 
and does not indicate cache position like in RDT. 
Sector is a group of cache ways, and one cache line cannot be assigned 
to different sectors at the same time. Different sectors have different 
cache space. When different tasks use different sectors, 
the cache space used can be isolated.

> >> 2.In RDT, L3 cache is shared among cores in socket. If two cores which
> >>    share L3 cache belongs to different resource groups, one resource
> >>    group's L3 setting will affect to other resource group's L3 setting?
> 
> This question is not entirely clear to me. Are you referring to the hardware layout
> or configuration changes via the resctrl "cpus" file?
> 
> Each resource group is a class of service (CLOS) that is supported by all cache
> instances. By default each resource group would thus contain all cache
> instances on the system (even if some cache instances do not support the
> same number of CLOS resctrl would only support the CLOS supported by all
> resources).

[Idea for A64FX sector cache function control]  
An example of using the sector function when working on resctrl 
as follows. 
  # mount -t resctrl resctrl /sys/fs/resctrl
  # cd /sys/fs/resctrl
  # mkdir p0
  # echo XXXX > /sys/fs/resctrl/p0/cpus *1 
  # echo “L1:0=000F,000F,000F,000F;1=000F,000F,000F,000F” > /sys/fs/resctrl/p0/schemata*2
  # echo “L2:0=000F,000F,0,0;1=0,0,000F,000F” > /sys/fs/resctrl/p0/schemata※2 
  # echo PID > sys/fs/resctrl/p0/tasks

*1 
   Since the A64FX L2 settings are shared by NUMA, all PEs (cores) 
   on the same NUMA should be specified at the same time. 
   In other words, we want to specify NUMAs instead of PEs to the 
   resource group. Maybe it is better to change the interface to 
   numas(/sys/fs/resctrl/p0/numas). Could you give me some advice? 
*2 
   L1:<cache_id0>=<cwbm>,<cwbm>,<cwbm>,<cwbm>;<cache_id1>=<cwbm>,<cwbm>,<cwbm>,<cwbm>;… 
   L2:<cache_id0>=<cwbm>,<cwbm>,<cwbm>,<cwbm>;<cache_id1>=<cwbm>,<cwbm>,<cwbm>,<cwbm>;… 
  ・ L1:
     Add a new interface to control the L1D cache. 
  ・ <cwbm>,<cwbm>,<cwbm>,<cwbm>:
     Specify the number of ways for each sector.  
     Each L1/L2 cache has 4 sectors.
     And it is needed to specify the number of ways for each sector. 
  ・ cwbm：
     Specify the number of ways in each sector as a bitmap (percentage), 
     but the bitmap does not indicate the position of the cache. 
     The range is from 0 way to 16 ways. 

When creating a resource group, the number of ways for 4 sectors of 
L1&L2 is set. When running a task, the [56:57] bits of virtual 
address are used for sector selection. Even different tasks running 
in the same resource group can use different sector caches. Therefore, 
when running a task that handles a large amount of infrequently used 
data and a task that handles a large amount of frequently used data 
at the same time, cache size limitation and cache space isolation can 
be performed, and cache thrashing also can be reduced. 

Is this approach acceptable? Could you give me some advice?  

Best regards,
Tan Shaopeng