[PATCH v1 01/13] arm64: Do not enable uaccess for flush_icache_range

[Mark Rutland]

On Wed, May 12, 2021 at 11:29:53AM +0100, Fuad Tabba wrote:
> Hi Mark,
> 
> On Wed, May 12, 2021 at 10:59 AM Mark Rutland <mark.rutland at arm.com> wrote:
> >
> > On Wed, May 12, 2021 at 09:52:28AM +0100, Fuad Tabba wrote:
> > > Hi Mark,
> > >
> > > > > No functional change intended.
> > > >
> > > > There is a performance change here, since the existing
> > > > `__flush_cache_user_range` takes IDC and DIC into account, whereas
> > > > `invalidate_icache_by_line` does not.
> > >
> > > You're right. There is a performance change in this patch and a couple
> > > of the others, which I will note in v2. However, I don't think that
> > > this patch changes the behavior when it comes to IDC and DIC, does it?
> >
> > It shouldn't be a functional problem, but it means that the new
> > `__flush_icache_range` will always perform redundant I-cache maintenance
> > rather than skipping this when the cpu has DIC=1.
> 
> Sorry, but I can't quite see how this patch is making a difference in
> that regard. The existing code has __flush_icache_range fallthrough to
> __flush_cache_user_range, where the alternative_if
> ARM64_HAS_CACHE_{IDC,DIC} are invoked.
> 
> In this patch, __flush_icache_range and __flush_cache_user_range share
> the same code via the macro, where the alternative_ifs and branches
> over invalidate_icache_by_line are still there and behave the same:
> the macro jumps to 8 if ARM64_HAS_CACHE_DIC, avoiding any redundant
> cache maintenance.
> 
> Am I missing something else?

No; you're absolutely right. I had misread the patch and thought the
IDC/DIC parts didn't go into the common macro. That all looks fine.

Sorry again for the noise.

Thanks,
Mark.