[PATCH 2/3] arm64: acpi: Map EFI_MEMORY_WT memory as Normal-NC

[Catalin Marinas]

On Thu, May 06, 2021 at 12:14:55PM +0200, Ard Biesheuvel wrote:
> On Thu, 6 May 2021 at 11:50, Will Deacon <will at kernel.org> wrote:
> >
> > The only user we have of Normal Write-Through memory is in the ACPI code
> > when mapping memory regions advertised as EFI_MEMORY_WT. Since most (all?)
> > CPUs treat write-through as non-cacheable under the hood, don't bother
> > with the extra memory type here and just treat EFI_MEMORY_WT the same way
> > as EFI_MEMORY_WC by mapping it to the Normal-NC memory type instead.
> >
> > Cc: Ard Biesheuvel <ardb at kernel.org>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> > Cc: Christoph Hellwig <hch at lst.de>
> > Signed-off-by: Will Deacon <will at kernel.org>
> 
> I don't have any objections to this change per se, but I will point
> out that the UEFI spec describes the MAIR encodings, paragraph 2.3.6.1
> (in revision 2.8B). However, the paragraph in question provides no
> context whatsoever, and so it is not clear whether it is normative,
> and whether it applies to the boot time firmware only or to the OS as
> well.
> 
> So in summary, given that EFI_MEMORY_WT (which I have never seen being
> used on ARM) should behave as expected when using the same MAIR
> attributes as EFI_MEMORY_WC, with only a theoretical performance
> impact, the change looks reasonable to me.

In theory there's a slight difference between WT and WC/Normal-NC as
reads are allowed to hit into the cache while for WC/Normal-NC they
aren't (somehow implied on page B2-168 in the ARMv8 ARM G.a). Whether
they must hit in the cache is not entirely clear, I don't think they
have to. The mismatched aliases section doesn't guarantee coherency
between accesses using different WC and WB attributes (point 1,
attributes must be the same for both reads and writes). Appendix K4.1.1
also suggest that WT could be implemented as Normal-NC.

So I don't think EFI can rely on any specific WT behaviour other than
maybe slightly better performance.

So:

Acked-by: Catalin Marinas <catalin.marinas at arm.com>