[PATCH net-next 1/3] arm64: barrier: add DGH macros to control memory accesses merging

[huangguangbin (A)]

On 2021/6/22 20:32, Mark Rutland wrote:
> On Tue, Jun 22, 2021 at 01:16:31PM +0100, Will Deacon wrote:
>> On Tue, Jun 22, 2021 at 07:11:09PM +0800, Guangbin Huang wrote:
>>> From: Xiongfeng Wang <wangxiongfeng2 at huawei.com>
>>>
>>> DGH prohibits merging memory accesses with Normal-NC or Device-GRE
>>> attributes before the hint instruction with any memory accesses
>>> appearing after the hint instruction. Provide macros to expose it to the
>>> arch code.
>>
>> Hmm.
>>
>> The architecture states:
>>
>>    | DGH is a hint instruction. A DGH instruction is not expected to be
>>    | performance optimal to merge memory accesses with Normal Non-cacheable
>>    | or Device-GRE attributes appearing in program order before the hint
>>    | instruction with any memory accesses appearing after the hint instruction
>>    | into a single memory transaction on an interconnect.
>>
>> which doesn't make a whole lot of sense to me, in all honesty.
> 
> I think there are some missing words, and this was supposed to say
> something like:
> 
> | DGH is a hint instruction. A DGH instruction *indicates that it* is
> | not expected to be performance optimal to merge memory accesses with
> | Normal Non-cacheable or Device-GRE attributes appearing in program
> | order before the hint instruction with any memory accesses appearing
> | after the hint instruction into a single memory transaction on an
> | interconnect.
> 
> ... i.e. it's a hint to the CPU to avoid merging accesses which are
> either side of the DGH, so that the prior accesses don't get
> indefinitely delayed waiting to be merged.
> 
> I'll try to get the documentation fixed, since as-is the wording does
> not make sense.
> 
> Thanks,
> Mark.
> .
> 
Thanks very much, we will fix the documentation.

Thanks,
Guangbin,
.