[PATCH] i2c: cadence: Clear HOLD bit before xfer_size register rolls over

[Wolfram Sang]

On Tue, Nov 24, 2020 at 01:16:05PM +0530, Raviteja Narayanam wrote:
> On Xilinx zynq SOC if the delay between address register write and
> control register write in cdns_mrecv function is more, the xfer size
> register rolls over and controller is stuck. This is an IP bug and
> is resolved in later versions of IP.
> 
> To avoid this scenario, disable the interrupts on the current processor
> core between the two register writes and enable them later. This can
> help achieve the timing constraint.
> 
> Signed-off-by: Raviteja Narayanam <raviteja.narayanam at xilinx.com>

Applied to for-next, thanks!

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