[PATCH v1 2/3] coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer

[Suzuki K Poulose]

Hi Leo

On 28/05/2021 17:15, Leo Yan wrote:
> When enable the Arm CoreSight PMU event, the context for AUX ring buffer
> is prepared in the structure perf_output_handle, and its field "head"
> points the head of the AUX ring buffer and it is updated after filling
> AUX trace data into buffer.
> 
> Current code uses an extra field etr_perf_buffer::head to maintain the
> header for the AUX ring buffer, thus it's not necessary and it's better
> to directly perf_output_handle::head.
> 
> This patch removes the header etr_perf_buffer::head and directly used
> perf_output_handle::head as the header for AUX ring buffer.
> 
> Signed-off-by: Leo Yan <leo.yan at linaro.org>
> ---
>   drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 +++-------
>   1 file changed, 3 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index acdb59e0e661..b22823d67680 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -32,7 +32,6 @@ struct etr_flat_buf {
>    * @etr_buf		- Actual buffer used by the ETR
>    * @pid			- The PID this etr_perf_buffer belongs to.
>    * @snaphost		- Perf session mode
> - * @head		- handle->head at the beginning of the session.
>    * @nr_pages		- Number of pages in the ring buffer.
>    * @pages		- Array of Pages in the ring buffer.
>    */
> @@ -41,7 +40,6 @@ struct etr_perf_buffer {
>   	struct etr_buf		*etr_buf;
>   	pid_t			pid;
>   	bool			snapshot;
> -	unsigned long		head;
>   	int			nr_pages;
>   	void			**pages;
>   };
> @@ -1437,16 +1435,16 @@ static void tmc_free_etr_buffer(void *config)
>    * buffer to the perf ring buffer.
>    */
>   static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
> +				     unsigned long head,
>   				     unsigned long src_offset,
>   				     unsigned long to_copy)
>   {
>   	long bytes;
>   	long pg_idx, pg_offset;
> -	unsigned long head = etr_perf->head;
>   	char **dst_pages, *src_buf;
>   	struct etr_buf *etr_buf = etr_perf->etr_buf;
>   
> -	head = etr_perf->head;
> +	head = PERF_IDX2OFF(head, etr_perf);
>   	pg_idx = head >> PAGE_SHIFT;
>   	pg_offset = head & (PAGE_SIZE - 1);
>   	dst_pages = (char **)etr_perf->pages;
> @@ -1553,7 +1551,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
>   	/* Insert barrier packets at the beginning, if there was an overflow */
>   	if (lost)
>   		tmc_etr_buf_insert_barrier_packet(etr_buf, offset);
> -	tmc_etr_sync_perf_buffer(etr_perf, offset, size);
> +	tmc_etr_sync_perf_buffer(etr_perf, handle->head, offset, size);
>   
>   	/*
>   	 * In snapshot mode we simply increment the head by the number of byte
> @@ -1605,8 +1603,6 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data)
>   		goto unlock_out;
>   	}
>   
> -	etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf);
> -
>   	/*
>   	 * No HW configuration is needed if the sink is already in
>   	 * use for this session.
> 

This looks good to me and could avoid any potential issues
with stale offset cached in the etr_perf_buffer.

Reviewed-by: Suzuki K Poulose <suzuki.poulose at arm.com>